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IT8661F
Plug and Play Super AT I/O
Preliminary Specification V0.6
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Copyright
(c)1998 ITE, Inc.
This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE' s Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT8661F is a trademark of ITE, Inc. Intel, Pentium, and MMX are claimed as trademarks by Intel Corp. Cyrix, M1, and SLiC/MP are claimed as trademarks by Cyrix Corp. AMD, AMD-K5, and AMD-K6 are claimed as trademarks by Advanced Micro Devices, Inc. Microsoft and Windows are claimed as trademarks by Microsoft Corporation. PCI is claimed as a trademark by the PCI Special Interest Group. IrDA is claimed as a trademark by the Infrared Data Association. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE (USA) Inc. Phone: (408) 530-8860 Marketing Department Fax: (408) 530-8861 1235 Midas Way Sunnyvale, CA 94086 U.S.A. ITE (USA) Inc. Eastern U.S.A. Sales Office 896 Summit St., #105 Round Rock, TX 78664 U.S.A. ITE, Inc. Marketing Department 7F, No. 435, Jui Kuang RD., Taipei 114, Taiwan, R.O.C Phone: (512) 388-7880 Fax: (512) 388-3108
Phone: (02) 2657-9896 Fax: (02) 2657-8561, 2657-8576
If you have any marketing or sales questions, please contact: Lawrence Liu, at ITE Taiwan: E-mail: lawrence.liu@ite.com.tw, Tel: 886-2-26579896 X6071, Fax: 886-2-26578561 David Lin, at ITE U.S.A: E-mail: david.lin@iteusa.com, Tel: (408) 980-8168 X238, Fax: (408) 980-9232 Don Gardenhire, at ITE Eastern USA Office: E-mail: don.gardenhire@iteusa.com, Tel: (512) 388-7880, Fax: (512) 388-3108 To find out more about ITE, visit our World Wide Web at: http://www.iteusa.com http://www.ite.com.tw Or e-mail itesupport@ite.com.tw for more product information/services.
CONTENTS
Page 1. 2. 3. 4. 5. 6. Features ................................................................................................................................................ 1 General Description.............................................................................................................................. 3 Pin Configuration ................................................................................................................................. 3 Block Diagram ...................................................................................................................................... 4 IT8661F Pin Descriptions ..................................................................................................................... 5 Configuring Sequence Description ..................................................................................................... 9 6.1 6.2 6.3 6.4 6.5 General Description ......................................................................................................................... 9 MB PnP Mode ............................................................................................................................... 10 ISA PnP Mode ............................................................................................................................... 10 Plug and Play Operation Sequence ............................................................................................... 12 Description of the Configuration Registers ..................................................................................... 13 Logical Device Base Address.................................................................................................. 17
6.5.1 6.6
Global Configuration Registers (LDN: All) ...................................................................................... 18 Set RD_DATA Port (Index=00h, ISA PnP) .............................................................................. 18 Serial Isolation (Index=01h, ISA PnP) ..................................................................................... 18 Configure Control (Index=02h, ISA PnP/MB PnP)................................................................... 18 Wake[CSN] (Index=03h, ISA PnP).......................................................................................... 18 Resource Data (Index=04h, ISA PnP)..................................................................................... 18 Status (Index=05h, ISA PnP) .................................................................................................. 18 Card Select Number (CSN, Index=06h, Default=00h, ISA PnP) .............................................. 18 Logical Device Number (LDN, Index=07h, ISA PnP/MB PnP)................................................. 18 Chip ID Byte 1 (Index=20h, Default=86h, MB PnP)................................................................. 18 Chip ID Byte 2 (Index=21h, Default=61h, MB PnP)................................................................. 18 Chip Version & Multi-Chips Clarification (Index=22h, Default=00h, MB PnP) .......................... 18 PnP Logical Device Enable Register (Index=23h, Default=00h, MB PnP) ............................... 19 Software Suspend and Input Clock Select (Index=24h, Default=00h, MB PnP) ....................... 19 GPIO Function Enable Registers[12:8] (Index=25h, Default=00h, MB PnP) ............................ 19 GPIO Function Pin Enable Register[7:0] (Index=26h, Default=00h, MB PnP) ......................... 19
6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 6.6.10 6.6.11 6.6.12 6.6.13 6.6.14 6.6.15 6.7
FDC Configuration Registers (LDN=00h) ....................................................................................... 20 FDC Activate (Index=30h, Default=00h, ISA PnP/MB PnP) .................................................... 20 FDC I/O Range Check (Index=31h, Default=00h, ISA PnP) .................................................... 20 FDC Base Address MSB Register (Index=60h, Default=03h, ISA PnP/MB PnP) ..................... 20 FDC Base Address LSB Register (Index=61h, Default=F0h, ISA PnP/MB PnP)...................... 20 FDC Interrupt Level Select (Index=70h, Default=06h, ISA PnP/MB PnP)................................ 20 FDC Interrupt Type (Index=71h, Default=02h, ISA PnP) ......................................................... 20 FDC DMA Channel Select (Index=74h, Default=02h, ISA PnP/MB PnP)................................. 20 FDC Special Configuration Register (Index=F0h, Default=00h, MB PnP)................................ 21
6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.7 6.7.8
i
6.8
Serial Port 1 Configuration Registers (LDN=01h) ........................................................................... 21 Serial Port 1 Activate (Index=30h, Default=00h, ISA PnP/MB PnP) ........................................ 21 Serial Port 1 I/O Range Check (Index=31h, Default=00h, ISA PnP)........................................ 21 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h, ISA PnP/MB PnP)......... 21 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h, ISA PnP/MB PnP).......... 21 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h, ISA PnP/MB PnP).................... 21 Serial Port 1 Interrupt Type (Index=71h, Default=02h, ISA PnP)............................................. 21 Serial Port 1 Special Configuration Register (Index=F0h, Default=00h, MB PnP).................... 21
6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 6.8.7 6.9
Serial Port 2 Configuration Registers (LDN=02h) ........................................................................... 22 Serial Port 2 Activate (Index=30h, Default=00h, ISA PnP/MB PnP) ........................................ 22 Serial Port 2 I/O Range Check (Index=31h, Default=00h, ISA PnP)........................................ 22 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h, ISA PnP/MB PnP)......... 22 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h, ISA PnP/MB PnP).......... 22 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h, ISA PnP/MB PnP).................... 22 Serial Port 2 Interrupt Type (Index=71h, Default=02h, ISA PnP)............................................. 22 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h, MB PnP)................. 22
6.9.1 6.9.2 6.9.3 6.9.4 6.9.5 6.9.6 6.9.7 6.10
Parallel Port Configuration Registers (LDN=03h) ........................................................................... 23 Parallel Port Activate (Index=30h, Default=00h, ISA PnP/MB PnP) ........................................ 23 Parallel Port I/O Range Check (Index=31h, Default=00h, ISA PnP) ........................................ 23 Parallel Port Base Address 1 MSB Register (Index=60h, Default=03h, ISA PnP/MB PnP) ...... 23 Parallel Port Base Address 1 LSB Register (Index=61h, Default=78h, ISA PnP/MB PnP) ....... 23 Parallel Port Base Address 2 MSB Register (Index=62h, Default=07h, ISA PnP/MB PnP) ...... 23 Parallel Port Base Address 2 LSB Register (Index=63h, Default=78h, ISA PnP/MB PnP) ....... 23 Parallel Port Interrupt Level Select (Index=70h, Default=07h, ISA PnP/MB PnP).................... 23 Parallel Port Interrupt Type (Index=71h, Default=02h, ISA PnP) ............................................. 23 Parallel Port DMA Channel Select (Index=74h, Default=03h, ISA PnP/MB PnP)..................... 24 Parallel Port Special Configuration Register (Index=F0h, Default=03h, MB PnP) ................ 24
6.10.1 6.10.2 6.10.3 6.10.4 6.10.5 6.10.6 6.10.7 6.10.8 6.10.9 6.10.10 6.11
IR Configuration Registers (LDN=04h)........................................................................................... 24 IR Activate (Index=30h, Default=00h, ISA PnP/MB PnP) ........................................................ 24 IR I/O Range Check (Index=31h, Default=00h, ISA PnP)........................................................ 24 IR Base Address 1 MSB Register (Index=60h, Default=02h, ISA PnP/MB PnP)...................... 24 IR Base Address 1 LSB Register (Index=61h, Default=E8h, ISA PnP/MB PnP) ...................... 24 IR Base Address 2 MSB Register (Index=62h, Default=03h, ISA PnP/MB PnP)...................... 24 IR Base Address 2 LSB Register (Index=63h, Default=00h, ISA PnP/MB PnP)....................... 25 IR Interrupt Level Select 1 (Index=70h, Default=0Ah, ISA PnP/MB PnP) ................................ 25 IR Interrupt Type 1 (Index=71h, Default=02h, ISA PnP).......................................................... 25 IR Interrupt Level Select 2 (Index=72h, Default=0Bh, ISA PnP/MB PnP) ................................ 25 IR Interrupt Type 2 (Index=73h, Default=02h, ISA PnP) ...................................................... 25 IR DMA Channel Select 1 (Index=74h, Default=01h, ISA PnP/MB PnP).............................. 25 ii
6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.11.7 6.11.8 6.11.9 6.11.10 6.11.11
6.11.12 6.11.13 6.12
IR DMA Channel Select 2 (Index=75h, Default=00h, ISA PnP/MB PnP).............................. 25 IR Special Configuration Register (Index=F0h, Default=00h, MB PnP)................................ 26
GPIO & Alternate Function Configuration Registers (LDN=05h)..................................................... 26 CS0 Base Address MSB Register (Index=60h, Default=00h, MB PnP).................................... 26 CS0 Base Address LSB Register (Index=61h, Default=00h, MB PnP)..................................... 26 CS1 Base Address MSB Register (Index=62h, Default=00h, MB PnP).................................... 26 CS1 Base Address LSB Register (Index=63h, Default=00h, MB PnP)..................................... 26 CS2 Base Address MSB Register (Index=64h, Default=00h, MB PnP).................................... 26 CS2 Base Address LSB Register (Index=65h, Default=00h, MB PnP)..................................... 26 Simple I/O Base Address MSB Register (Index=66h, Default=00h, MB PnP).......................... 27 Simple I/O Base Address LSB Register (Index=67h, Default=00h, MB PnP)........................... 27 GPIO Interrupt Level Select (Index=70h, Default=00h, MB PnP) ............................................ 27 GPIO[7:0] Pin Polarity Register (Index=F0h, Default=00h, MB PnP) ................................... 27 CS0/CS1/CS2 Control Register (Index=F1h/F2h/F3h, Default=00h, MB PnP) ..................... 27 GPIO[7:0] Function Selection Register (Index=F4h, Default=00h, MB PnP) ........................ 27 Simple I/O[7:0] Direction Selection Register (Index=F5h, Default=00h, MB PnP) ................ 27
6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9 6.12.10 6.12.11 6.12.12 6.12.13
6.12.14 Zero Wait State Control & On-Chip High Address Qualification Enable Register (Index=F6h, Default=00h, MB PnP).......................................................................................................................... 28 6.12.15 6.12.16 6.12.17 6.12.18 Device Zero Wait State Enable Register (Index=F7h, Default=00h, MB PnP) ..................... 28 GPIO[12:8] Pin Polarity Register (Index=F8h, Default=00h, MB PnP) ................................. 28 GPIO[12:8] Function Selection Register (Index=F9h, Default=00h, MB PnP) ...................... 28 Simple I/O[12:8] Direction Selection Register (Index=FAh, Default=00h, MB PnP).............. 28
6.12.19High Address Qualification Inputs 1 & 2 Selection Register (Index=FBh, Default = 00h, MB PnP)29 6.12.20High Address Qualification Inputs 3 & 4 Selection Register (Index=FCh, Default = 00h, MB PnP)29 7. Functional Description....................................................................................................................... 30 7.1 7.2 General Purpose I/O...................................................................................................................... 30 FDC Register Description .............................................................................................................. 32 Digital Output Register (DOR) - (Base Address + 02h)............................................................ 32 Main Status Register (MSR) - (Base Address + 04h)............................................................... 32 Data Register (FIFO) - (Base Address + 05h).......................................................................... 33 Digital Input Register (DIR) - (Base + 07h) .............................................................................. 33 Diskette Control Register (DCR) - (Base Address + 07h WRITE) ............................................ 33 Status Register ....................................................................................................................... 34 Reset ...................................................................................................................................... 36 Controller Phases ................................................................................................................... 36 Data Transfer Commands Description .................................................................................... 36
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.3
Serial Channel Register Description............................................................................................... 49 Data Register.......................................................................................................................... 49 Control Registers: IER, IIR, FCR, DLL, DLM, LCR, MCR ........................................................ 49 Status Register LSR and MSR ................................................................................................ 51 iii
7.3.1 7.3.2 7.3.3
7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.4
Reset ...................................................................................................................................... 53 Programming.......................................................................................................................... 55 Software Reset ....................................................................................................................... 55 Clock Input Operation ............................................................................................................. 55 FIFO Interrupt Mode Operation............................................................................................... 55
Parallel Port................................................................................................................................... 55 SPP and EPP Modes.............................................................................................................. 55 EPP Mode Operation .............................................................................................................. 56 ECP Mode Operation.............................................................................................................. 57
7.4.1 7.4.2 7.4.3 8. 9.
DC Electrical Characteristics ............................................................................................................. 67 AC Characteristics ( VCC = 5.0V 5%, Ta = 0C to + 70C) ............................................................. 69 9.1 9.2 9.3 READ Cycle Timing....................................................................................................................... 69 WRITE Cycle Timing ..................................................................................................................... 69 FDC Timing ................................................................................................................................... 70 DMA Operation Timing ........................................................................................................... 70 Terminal Count, Index ............................................................................................................ 70 FDD WRITE/READ Operation Timing..................................................................................... 71 SEEK Operation Timing.......................................................................................................... 71
9.3.1 9.3.2 9.3.3 9.3.4 9.4
Serial Port Timing.......................................................................................................................... 72 Transmitter ............................................................................................................................. 72 Modem ................................................................................................................................... 73 Receiver ................................................................................................................................. 74 IrDA Receive Timing............................................................................................................... 74 IrDA Transmit Timing.............................................................................................................. 75 ASKIR Receive Timing ........................................................................................................... 75 ASKIR Transmit Timing .......................................................................................................... 76
9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.5
Parallel Port Timing ....................................................................................................................... 76 Control Signal Delay Time ...................................................................................................... 76 Interrupt Request Timing ........................................................................................................ 77
9.5.1 9.5.2 9.6 9.7 9.8 9.9
EPP Address or DATA WRITE Cycle............................................................................................. 78 EPP Address or DATA READ Cycle .............................................................................................. 79 ECP Parallel Port Forward Timing Diagram ................................................................................... 80 ECP Parallel Port Backward Timing Diagram ................................................................................ 81
10. Package Information .......................................................................................................................... 82 11. Ordering Information.......................................................................................................................... 83
iv
TABLES
Page Table 5-1. Signal Names (by pin numbers in alphabetical order).................................................................... 5 Table 5-2. Signal Names (by pin numbers in alphabetical order) [cont'd] ....................................................... 6 Table 5-3. Signal Names (by pin numbers in alphabetical order) [cont'd] ....................................................... 7 Table 5-4. Signal Names (by pin numbers in alphabetical order) [cont'd] ....................................................... 8 Table 6-1. Global Configuration Registers ................................................................................................... 13 Table 6-2. FDC Configuration Registers ...................................................................................................... 14 Table 6-3. Serial Port 1 Configuration Registers .......................................................................................... 14 Table 6-4. Serial Port 2 Configuration Registers .......................................................................................... 14 Table 6-5. Parallel Port Configuration Registers .......................................................................................... 15 Table 6-6. IR Configuration Registers .......................................................................................................... 15 Table 6-7. GPIO & Alternate Function Configuration Registers .................................................................... 16 Table 6-8. Base Address of Logical Devices ................................................................................................ 17 Table 7-1. Digital Output Register (DOR)..................................................................................................... 32 Table 7-2. Main Status Register (MSR)........................................................................................................ 32 Table 7-3. Digital Input Register (DIR) ......................................................................................................... 33 Table 7-4. Diskette Control Register (DCR) ................................................................................................. 33 Table 7-5. Status Register 0 ........................................................................................................................ 34 Table 7-6. Status Register 1 ........................................................................................................................ 34 Table 7-7. Status Register 2 ........................................................................................................................ 35 Table 7-8. Status Register 3 ........................................................................................................................ 35 Table 7-9. Command Symbol Description.................................................................................................... 37 Table 7-10. Effects of MT and N Bits ........................................................................................................... 39 Table 7-11. Description of the READ DATA Command................................................................................ 39 Table 7-12. Description of the READ DELETED DATA Command............................................................... 40 Table 7-13. Description of the READ A TRACK Command.......................................................................... 41 Table 7-14. Description of the WRITE DATA Command.............................................................................. 42 Table 7-15. Description of the WRITE DELETED DATA Command............................................................. 43 Table 7-16. Description of the FORMAT A TRACK Command..................................................................... 44 Table 7-17. Description of the READ ID Command...................................................................................... 45 Table 7-18. Description of the RE-CALIBRATE Command .......................................................................... 45 Table 7-19. Description of the SEEK Command .......................................................................................... 46 Table 7-20. Interrupt Identification of the SENSE INTERRUPT STATUS Command.................................... 47 Table 7-21. Description of the SENSE INTERRUPT STATUS Command .................................................... 47 Table 7-22. Description of the SENSE DRIVE STATUS Command ............................................................. 47 Table 7-23. Description of the SPECIFY Command..................................................................................... 48 Table 7-24. Description of the INVALID Command ...................................................................................... 48 Table 7-25. Serial Channel Registers........................................................................................................... 49 v
Table 7-26. Interrupt Identification Register ................................................................................................. 50 Table 7-27. Baud Rates Using (24MHz / 13) Clock ..................................................................................... 51 Table 7-28. Modem Control Register Bits .................................................................................................... 51 Table 7-29. Line Status Register Bits ........................................................................................................... 52 Table 7-30. Modem Status Register Bits...................................................................................................... 53 Table 7-31. Reset Control of Registers and Pinout Signals .......................................................................... 53 Table 7-32. Parallel Port Connector in Different Modes ............................................................................... 55 Table 7-33. Address Map and Bit Map for SPP and EPP Modes.................................................................. 55 Table 7-34. Bit Map of the ECP Registers.................................................................................................... 58 Table 7-35. ECP Register Definitions........................................................................................................... 58 Table 7-36. ECP Mode Descriptions ............................................................................................................ 59 Table 7-37. ECP Pin Descriptions................................................................................................................ 59 Table 7-38. Extended Control Register (ECR) Mode and Description........................................................... 61 Table 9-1. READ Cycle Timing .................................................................................................................... 69 Table 9-2. WRITE Cycle Timing .................................................................................................................. 69 Table 9-3. DMA Operation Timing of FDC Timing ....................................................................................... 70 Table 9-4. Terminal Count, Index of FDC Timing......................................................................................... 70 Table 9-5. FDD WRITE/READ Operation Timing of FDC Timing................................................................. 71 Table 9-6. SEEK Operation Timing of FDC Timing...................................................................................... 71 Table 9-7. Transmitter of Serial Port Timing ................................................................................................ 72 Table 9-8. Modem of Serial Port Timing ...................................................................................................... 73 Table 9-9. Receiver of Serial Port Timing .................................................................................................... 74 Table 9-10. IrDA Receive Timing of Serial Port Timing................................................................................ 74 Table 9-11. IrDA Transmit Timing of Serial Port Timing............................................................................... 75 Table 9-12. ASKIR Receive Timing of Serial Port Timing ............................................................................ 76 Table 9-13. ASKIR Transmit Timing of Serial Port Timing ........................................................................... 76 Table 9-14. Control Signal Delay Time of Parallel Port Timing .................................................................... 77 Table 9-15. Interrupt Request Timing of Parallel Port Timing....................................................................... 77 Table 9-16. EPP Address or DATA WRITE Cycle........................................................................................ 78 Table 9-17. EPP Address or DATA READ Cycle.......................................................................................... 80 Table 9-18. ECP Parallel Port Forward Timing ............................................................................................ 81 Table 9-19. ECP Parallel Port Backward Timing .......................................................................................... 81
vi
FIGURES
Page Figure 6-1. Configuration Sequence Flow Chart............................................................................................. 9 Figure 6-2. PnP State Transition.................................................................................................................. 11 Figure 7-1. General Logic of GPIO Function................................................................................................ 31
vii
IT8661F
Preliminary V0.6 Specifications are subject to Change without Notice
Plug and Play Super AT I/O
ITPA-PN-97014, W.B., Apr. 18, 1998
1. Features
g
PC97/98 Compliant Hardware (PC99 Ready) - Unique PnP device ID for each logical device compliant with Plug and Play specification V1.0a - Built-in resource data ROM - Five logical devices - 16-bit address decoding - Seven selectable IRQs - Four selectable DMA channels - Flexible resource configure and dynamic disable - IRQ sharing supported 2.88MB Floppy Disk Controller - Base address 0x0100h-0x0FF8h, seven IRQ and four DMA options - 48mA direct output driver - Enhanced digital data separator - A and B drives can be logically swapped via registers - 3-mode drives supported - Supports automatic write protection via software - Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy disk drives Multi-mode High Performance Parallel Port - Base address 0x0100h-0x0FFCh, seven IRQ and four DMA options - Standard mode -- bi-directional SPP - Enhanced mode -- EPP V. 1.7 and EPP V. 1.9 compliant - High Speed mode -- ECP, IEEE 1284 compliant - Backdrive current protection - Printer power-on damage protection
g Serial
Ports - Base address 0x100h-0x0FF8h, seven IRQ options - Supports two 16C550 standard compatible enhanced serial ports - Supports send/receive 16-byte FIFOs - MIDI standard compatible
g
g
Infrared Communication Controller - Base address 0x0100h-0x0FF8h, seven IRQ and four DMA options - Supports HPSIR or ASKIR infrared interface -Dedicated 16C550 standard UART supporting infrared communication - Back-to-back packet transmission Provides thirteen General Purpose I/O pins Only one 24MHz or 48MHz crystal needed 5-volt operation 100-pin QFP package
g g g g
g
1
IT8661F
2. General Description
The IT8661F Plug and Play Super AT I/O chip is a user-friendly, low cost peripheral controller. It provides an ideal solution for Microsoft PC97/98 (PC99 ready) system requirements. A programmable IRQ sharing function is supported to comply with Microsoft PC97/98 (PC99 ready) requirements. No N.V. memory is needed to store resource data for Plug and Play system applications. The IT8661F consists of five logical devices. One high performance 2.88MB floppy disk controller, with digital data separator, supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high performance Parallel Port features the bidirectional Standard Parallel Port (SPP), the Enhanced Parallel Port (EPP. V1.7 and v1.9 are supported), and IEEE 1284 compliant Extended Capabilities Port (ECP). Two 16C550 standard compatible enhanced UARTs perform asynchronous communication for serial ports. One highly integrated infrared communication controller is capable of supporting HPSIR, MIR, or ASKIR with a builtin dedicated 16C550 standard compatible UART. These five logical devices can be individually enabled or disabled via software configuration registers. The IT8661F utilizes power saving circuitry to reduce power consumption. Once a logical device is disabled, its related inputs are gate inhibited, outputs are tristated, and input clock is disabled. The Parallel Port includes a specifically designed circuit to reduce damage or backdrive current when a printer or another parallel port device is powered-on. In effect, the IT8661F is a highperformance, low-power consumption I/O device.
2
IT8661F
3. Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DENSEL# MOTEA# DRVB# DRVA# MOTEB# GND DIR# STEP# WDATA# WGATE# SIDE1# INDEX# TK00# WPT# VCC RDATA# DSKCHG# XTALO IRSOUT/GPIO10 XTALI DRQ1 DACK1# DRQ0 IRQ5 IRQ10/GPIO11 IRQ11/GPIO12 A11 A0 A1 A2
IOCHRDY DRQ3 IRSINH*/GPIO9 A10 DACK3# GND IRSINL/GPIO8 DTR2#/GPIO7 CTS2#/A12/GPIO6 RTS2#/GPIO5 DSR2#/A13/GPIO4 SOUT2/GPIO3 SIN2/GPIO2 RLSD2#/A14/GPIO1 RI2#/A15/GPIO0 RLSD1# RI1# DTR1#/MC0 CTS1# RTS1#/MC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
IT8661F
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DSR1# SOUT1 SIN1 AFD# STB# ERR# SLIN# INIT# VCC PD0 PD1 PD2 PD3 GND PD4 PD5 PD6 PD7 ACK# BUSY PE SLCT DACK0# RESET D7 D6 D5 D4 DRQ2 D3
A3 A4 A5 A6 TC DACK2# IRQ3 IRQ4 IRQ7 IRQ6 A7 A8 A9 IOR# IOW# AEN GND D0 D1 D2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3
IT8661F
4. Block Diagram
GPIO0 - 12
IOR#
GENERAL PURPOSE I/O
PD0-PD7 MULTI-MODE PARALLEL PORT BUSY, PE, SLCT, ACK#, ERR# STB#, AFD#, INIT#, SLIN#
IOW#
Data Bus
AEN
A0-A15 16C550 STANDARD COMPATIBLE SERIAL PORT PLUG AND PLAY CONFIGURATION CONTROL
SIN1, CTS1#, DSR1#, RLSD1#, RI1# DTR1#, RTS1#, SOUT1
D0-D7
IRQ3-7 IRQ10-11 DRQ0 | DRQ3 DACK0# | DACK3# HOST CPU I/F
(Control Bus)
16C550 STANDARD COMPATIBLE SERIAL PORT
SIN2, CTS2#, DSR2#, RLSD2#, RI2# DTR2#, RTS2#, SOUT2
TC
RESET
FLOPPY DISK CONTROLLER 16C550 STANDARD COMPATIBLE UART & FIR CONTROLLER
IRSINL IRSINH* IRSOUT
IOCHRDY
CLOCK GENERATOR
XTALI
XTALO
INDEX# TK00# WPT# RDATA# DSKCHG#
DENSEL#, MOTEA/B#, DRVA/B#, DIR# STEP#, WDATA#, WGATE#
4
IT8661F
5. IT8661F Pin Descriptions
Table 5-1. Signal Names (by pin numbers in alphabetical order) Pin No.
1 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 23, 21 52, 99 22, 58 36, 96 25
Signal
DENSEL# MOTEA# DRVB# DRVA# MOTEB# DIR# STEP# WDATA# WGATE# SIDE1# INDEX# TK00# WPT# RDATA# DSKCHG# XTALO IRSOUT/GPIO10 XTALI DRQ0 - 3
I/O
O48 O48 O48 O48 O48 O48 O48 O48 O48 O48 IS IS IS IS IS OCLK I/O24 ICLK OP12
Description
DENSEL# is high for high data rate (500 Kbps/1 Mbps) DENSEL# is low for low data rate (250/300 Kbps) FDD Motor A Enable, active low FDD Drive B Enable, active low FDD Drive A Enable, active low FDD Motor Enable, active low FDC Head Direction. Step in when low, step out when high during a SEEK operation. FDC Step Pulse Output to the drive during a SEEK operation, active low. FDC Write Serial Data to the drive, active low FDC Write Enable Identify, active low Floppy Disk Side 1 Select, active low FDC Index, active low. Indicates the beginning of a disk track. Floppy Disk Track 0, active low. Indicates that the head of the selected drive is on track 0. FDD Write Protect, active low. Indicates that the disk of the selected drive is write-protected. Read Disk Data, active low, serial data input from the FDD Floppy Disk Change, active low. This is an input pin that senses whether the drive door has been opened or a diskette has been changed. 24 MHz or 48 MHz Crystal Oscillator Output. If an external clock is used, this pin is left disconnected. Infrared data output of SIR. The second function is General Purpose I/O. 24 MHz or 48 MHz Crystal Oscillator Input. An external clock in use must be connected to this pin. DMA Request 0, 1, 2, 3. The logical devices of the IT8661F can be mapped to individual DRQx via configuration register(0x74). These signals are cleared by the going-low of DACK 0, 1, 2, and 3# signals. DMA Acknowledge 0, 1, 2, 3. The logical devices of the IT8661F can be mapped to individual DACKx. Interrupt Request 10. The logical devices of the IT8661F can be mapped to the individual IRQx via configuration register (0x70). The second function is General Purpose I/O. This pin is internally pulled up to 50K.
DACK0 - 3# IRQ10/GPIO11
IS OD24 I/O24
5
IT8661F
Table 5-2. Signal Names (by pin numbers in alphabetical order) [cont'd]
Pin No. 26 Signal IRQ11/GPIO12 I/O OD24 I/O24 Description Interrupt Request 11. The logical devices of the IT8661F can be mapped to the individual IRQx via configuration register (0x70). The second function is General Purpose I/O. This pin is internally pulled up to 50K.
97, 27, 41-43, 28-34 35 40, 39 37, 38 24 44 45 46 53-56 48-51 57
A0 - A11 TC IRQ3 - 7
IS IS OD24
12-bit I/O Address bus Terminal Count, active high to indicate that data transfer is completed Interrupt Request 3, 4, 5, 6, 7. The logical devices of the IT8661F can be mapped to the individual IRQx via configuration register (0x70). Read Strobe, active low Write Strobe, active low Address Enable, active high to indicate that the system is in DMA transfer mode 8-bit bi-directional data bus SYSTEM RESET, active high. At the falling edge of RESET, the voltage level of MC0 (pin 83) and MC1 (pin 81) are latched. Printer Select. This signal goes high when the line printer has been selected. Printer Paper End. This signal is set high by the printer when it runs out of paper. Printer Busy. This signal goes high when the line printer has a local operation in progress and cannot accept data. Printer Acknowledge. This signal goes low to indicate that the printer has already received a character and is ready to accept another. Parallel Port Data Bus. This bus provides a byte-wide input or output to the system. The eight 8 lines are held in high-impedance state when the port is deselected. Printer Initialize. Active low, this signal is derived from bit 2 of the printer control register, and is used to initialize printer.
IOR# IOW# AEN D0 - D7
IS IS IS I/O24
RESET
IS
59 60
SLCT PE
IS IS
61 62 68-71 63-66
BUSY ACK# PD7 - PD0
IS IS I/O24
73
INIT#
O24
6
IT8661F
Table 5-3. Signal Names (by pin numbers in alphabetical order) [cont'd]
Pin No. 75 Signal ERR# I/O IS Description Printer Error. Active low to indicate that the printer has encountered an error. The error message can be read from bit 3 of the printer status register. Printer Strobe. Active low, this signal is derived from the complement of bit 0 of the printer control register. It is used to strobe printer data into the printer. Printer Autofeed. Active low, this signal is derived from the complement of bit 1 of the printer control register. It is used to inform the printer to advance one line after previous lines are printed. Serial Port 1, Data Input. Serial Port 1, Data Output. Serial Port 1, Data Set Ready, active low. Serial Port 1, Request to Send Output, active low. During the hardware reset, this pin and pin 83 become input and DTR1# is tristated, then latches the voltage level of MC1 to clarify systems that use the same IT8661F I/O controller. (Refer to the general description of the configuring sequence on Page9.) Serial Port 1, Clear to Send Input, active low. Serial Port 1, Data Terminal Ready Output, active low. During the hardware reset, this pin and pin 81 become input and DTR1# is tristated, then latches the voltage level of MC0 to clarify systems that use the same IT8661F I/O controller. (Refer to the general description of the configuring sequence on Page 9.) Serial Port 1, Ring Indicator, active low. Serial Port 1, Receive Line Signal Detect, active low. Serial Port 2, Ring Indicator, active low. The second function is I/O Address 15. The third function is General Purpose I/O. This pin is internally pulled up to 50K. Serial Port 2, Receive Line Signal Detect, active low. The second function is I/O Address 14. The third function is General Purpose I/O. This pin is internally pulled up to 50K. Serial Port 2, Data Input. The second function is General Purpose I/O. This pin is internally pulled up to 50K. Serial Port 2, Data Output. The second function is General Purpose I/O. This pin is internally pulled up to 50K. Serial Port 2, Data Set Ready, active low. The second function is I/O Address 13. The third function is General Purpose I/O. This pin is internally pulled up to 50K.
76
STB#
O24
77
AFD#
O24
78 79 80
SIN1 SOUT1 DSR1#
IS O12 IS
81
RTS1#/MC1
O12/I
82
CTS1#
O12/I
83
DTR1#/MC0
O12/I
84 85
RI1# RLSD1#
IS IS
86
RI2#/A15/GPIO0
I/O12
87
RLSD2#/A14/ GPIO1 SIN2/GPIO2 SOUT2/GPIO3 DSR2#/A13/ GPIO4
I/O12
88 89 90
I/O12 I/O12 I/O12
7
IT8661F
Table 5-4. Signal Names (by pin numbers in alphabetical order) [cont'd]
Pin No. 91 92 93 94 Signal RTS2#/GPIO5 CTS2#/A12/GPIO6 DTR2#GPIO7 IRSINL/GPIO8 I/O12 I/O12 I/O12 Serial Port 2. Clear to Send Input, active low. The second function is I/O Address 12. The third function is General Purpose I/O. Serial Port 2, Data Terminal Ready Output, active low. The second function is General Purpose I/O. This pin is internally pulled up to 50K. The first function is one of the following: (1) Infrared data input pin or (2) Low frequency infrared data input pin of 2-input FIR transceiver (HP-like) or (3) Infrared data input pin of 1-input FIR transceiver (IBM-like). The second function is General Purpose I/O. This pin is internally pulled up to 50K. The IT8661F is a high-frequency infrared data input pin of 2-input FIR transceiver (HP-like) or mode select output pin of 1-input FIR transceiver (IBM-like). The second function is General Purpose I/O. This pin is internally pulled up 50K. EPP mode, pulled low to extend the READ/WRITE command +5V power pin Ground I/O Description
98
IRSINH*/GPIO9
OD12
100 15, 72 6, 47 67, 95
IOCHRDY VCC GND
OD24
8
IT8661F
6. Configuring Sequence Description
6.1 General Description After hardware reset or power-on reset, the IT8661F enters the normal mode with all logical devices disabled. There are two configuration modes for IT8661F: MB PnP mode and ISA PnP mode. The MC0 (pin 83) and MC1 (pin 81) are used to clarify different systems that use the same IT8661F I/O controller. In ISA PnP mode, the latched values of MC0 and MC1 can be used as the serial number LSB of to clarify different systems that use the same IT8661F I/O controller. In MB PnP mode, if bits 5 and 4 of global configuration register index 22h are written and the values of bits 5 and 4 equal the corresponding latch-reversed values of MC1 and MC0, then the MB PnP configuration mode can be entered. This can clarify different systems that use the same IT8661F I/O controller in MB PnP mode.
Hardware Reset Any other I/O transition cycle
Wait for key string
I/O write to 279h
Is the key port selected?
N
Y
Is the PnP protocal enabled?
N
N
Are the four consecutive bytes correct?
Y
Y
Save the I/O port as configuration port Is this the initial value of the initial key?
N
Y N
Does the data match first key? Wait for the next key
Y
Wait for the next key
Is this the next value in the key?
N
Y Y
I/O write to 279h?
N
Is this the last value in the key?
N N
Does the data match next key?
Y
ISA PnP Mode
Y
Does the data match last key?
N
Y
MB PnP Mode
Figure 6-1. Configuration Sequence Flow Chart
9
IT8661F
6.2 MB PnP Mode There are three steps to complete the configuration setup: (1) Enter the MB PnP mode; (2) Modify the data of configuration registers; (3) Exit the MB PnP mode. Unless normal exiting is done, the configuration setup may cause undesired results. (1) Enter the MB PnP Mode To enter the MB PnP mode, 36 special I/O write operations are to be performed during the Wait for Key state. To ensure the initial state of the key-check logic, it is first necessary to perform two write operations to Address port (279h) of the ISA PnP. The Entering Key includes two steps. The first FOUR bytes are used to determine the I/O address and data port of configuration register. If the other 32 bytes are not written properly and sequentially, it will cause a failure in the MB PnP mode while performing any IOR/IOW command to other I/O ports. To avoid this situation, we suggest that programmers disable interrupts while performing the 36 write operations. The corresponding sequential data for the first four bytes are:
I/O Address port 86h, 61h, 55h, 55h; or 86h, 61h, 55h, AAh; or 86h, 61h, AAh, 55h; 3F0h; 3BDh; 370h; Data port 3F1h 3BFh 371h
(2) Modify the Data of Configuration Registers After entering the MB PnP mode, all configuration registers can be accessed. However, modifying the data of the registers marked only for ISA PnP may cause undesired errors. Before the access to a selected register, the content of Index 07h must be changed to be consistent with the LDN to which the register belongs. Some registers, with Index 25h, 26h, 2Eh, and 2Fh, can be affected unless the last step is completed. (3) Exit the MB PnP mode Set bit 1 of the configure control register (Index 02h) to "1" to exit the MB PnP mode. 6.3 ISA PnP Mode This mode is ISA PnP standard compliant. (Please refer to Plug and Play, ISA Spec V1.0a for detailed descriptions.) In this mode, only some configuration registers of this chip can be accessed. The enable register for PnP logical device must be asserted prior to entering the MB PnP mode. Since the LDNs are dynamic, users can assign logical devices to be configured by ISA Plug and Play V1.0a protocol because they always remain enabled in PC systems and thus utilize fixed resources.
The sequential data for the other 32 bytes (same as the initial key of ISA PnP, but written to different I/O ports) are listed below in hexadecimal numeration: 6A, DF, B0, E8, B5, 6F, 58, 74, DA, 37, 2C, 3A, ED, 1B, 16, 9D, F6, 0D, 8B, CE, FB, 86, 45, E7, 7D, C3, A2, 73, BE, 61, D1 39
10
IT8661F
POWER UP RESET OR RESET COMMAND
SET CSN=0
STATE
ACTIVE COMMAND NO ACTIVE COMMANDS
WAIT FOR KEY
INITIATION KEY
(WAKE=0) AND (CSN=0)
STATE
ACTIVE COMMANDS RESET WAIT FOR KEY WAKE[CSN]
(WAKE<>0) AND (WAKE=CSN)
SLEEP
LOSE SERIAL ISOLATION OR (WAKE<>CSN)
(WAKE<>CSN)
STATE
ACTIVE COMMANDS
STATE
ACTIVE COMMANDS RESET WAIT FOR KEY WAKE[CSN] I/O RANGE CHECK ACTIVATE RESOURCE DATA STATUS LOGIC DEVICE CONFIGURE
ISOLATION
RESET WAIT FOR KEY WAKE[CSN] SET RD-DATA PORT SERIAL ISOLATION
SET CSN
CONFIG
Figure 6-2. PnP State Transition
11
IT8661F
6.4 Plug and Play Operation Sequence Refer to Figure 6-2. PnP State Transition. Here is an example of a procedure to be followed for IT8661F setup. It is optional and not the only sequence of events that may occur. For any state and at any time, all valid commands can be received and followed with proper feedback or response. a. At power-on or when the RESET signal is activated: - The Card Select Number (CSN) sets to "0X00". - All configuration registers for logical devices are set to their internal power-on default values. b. The Linear Feedback Shift Register (LFSR) is reset to its initial state (0X6A). c. Entering the "Wait for Key" state. The IT8661F enters this state within 1.5ms after RESET signal or RESET command. The initiation key is written to IT8661F. Each value of the initiation key is calculated after shifting the LFSR by one clock for each write, and the written data is compared with the calculated (expected) data. In this state, the chip will reset the LFSR to "0X6A" whenever it receives a write from the address port that does not match the current value in the LFSR. d. Once the initiation key is correctly received, the chip enters the "Sleep" state (the auto configuration ports are enabled.) e. The system sends a WAKE[CSN=0] command to switch the chip into the "Isolation" state. f. The system sets the RD_DATA port to an arbitrary address. g. The system performs the isolation protocol by sending a sequence of 72 pairs of I/O READ operations. (Refer to Hardware Protocol in ISA PnP Spec V1.0a.) h. Provided IT8661F passes the isolation protocol, the system sets the CSN to a non-zero value (assigned OUR_CSN) and IT8661F enters the "Configuration" state. I. The system reads the resource data from the IT8661F. j. The system switches IT8661F into "sleep" state by sending a "WWAKE" command with a CSN that is different from OUR_CSN. When IT8661F is in "Sleep" state, the system can perform operations from other Plug and Play chips. k. The system sends a WAKE[OUR_CSN]" command, and the IT8661F returns to the "Configuration" state. l. The system sets the logical device information and activates each of the logical devices. m. The system sends other commands. n. The system sends a """WAIT FOR KEY" command, and the IT8661F returns to the Wait for Key" state (the autoconfiguration ports are disabled). Notes: * At power-on or when the RESET signal is activated, go to step a. ** When a "WAIT FOR KEY"" command is received, go to step b.
12
IT8661F
6.5 Description of the Configuration Registers All the registers will be reset to the default state when RESET is activated. When the RESET command is asserted (configure control bit 0), the test registers and the registers which can be accessed during the ISA PnP mode, will be reset to their initial values (default values) in either the ISA PnP mode or the MB PnP mode; while the others (cannot be accessed during the ISA PnP mode) will be reset to the default values only in the MB PnP mode. Other registers with Index=22h, 23h, 24h, or 25h, are reset by the RESET command. Configuration Port Write-data Port 0X0279h 0X0A79h write-only write-only
Table 6-1. Global Configuration Registers LDN*1
All All All All All All All All All All All All All All-05h All-05h
*2 *2
Index
00h 01h 02h 03h 04h 05h 06h 07h 20h 21h 22h 23h 24h 25h 26h
R/W
W R W W R R R/W R/W R R R-R/W R/W R/W R-R/W R-R/W
Reset
NA NA NA NA NA NA 00h NA 86h 61h 00h 00h 00h 00h 00h
Access Mode
ISA PnP ISA PnP ISA PnP/MB PnP ISA PnP ISA PnP ISA PnP ISA PnP ISA PnP/MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP
Configuration Register or Action
Set RD_DATA port Serial Isolation Configure Control WAKE[CSN] Resource Data Status Card Select Number(CSN) Logical Device Number(LDN) Chip ID Byte 1 Chip ID Byte 2 Chip Version/Multi-chips clarification PnP Logical Device Enable Register SOFTWARE SUSPEND/Input Clock Select Register GPIO Function Enable Register[12:8] GPIO Function Enable Register[7:0]
13
IT8661F
Table 6-2. FDC Configuration Registers LDN*1
00h 00h 00h 00h 00h 00h 00h 00h
Index
30h 31h 60h 61h 70h 71h 74h F0h
R/W
R/W R/W R/W R/W R/W R R/W R/W
Reset
00h 00h 03h F0h 06h 02h 02h 00h
Access Mode
ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP MB PnP
Configuration Register or Action
FDC Activate FDC I/O Range Check FDC Base Address MSB Register FDC Base Address LSB Register FDC Interrupt Level Select FDC Interrupt Type FDC DMA Channel Select FDC Special Configuration Register
Table 6-3. Serial Port 1 Configuration Registers LDN*1
01h 01h 01h 01h 01h 01h 01h
Index
30h 31h 60h 61h 70h 71h F0h
R/W
R/W R/W R/W R/W R/W R R/W
Reset
00h 00h 03h F8h 04h 02h 00h
Access Mode
ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP MB PnP
Configuration Register or Action
Serial Port 1 Activate Serial Port 1 I/O Range Check Serial Port 1 Base Address MSB Register Serial Port 1 Base Address LSB Register Serial Port 1 Interrupt Level Select Serial Port 1 Interrupt Type Serial Port 1 Special Configuration Register
Table 6-4. Serial Port 2 Configuration Registers LDN*1
02h 02h 02h 02h 02h 02h 02h
Index
30h 31h 60h 61h 70h 71h F0h
R/W
R/W R/W R/W R/W R/W R R/W
Reset
00h 00h 02h F8h 03h 02h 00h
Access Mode
ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP MB PnP
Configuration Register or Action
Serial Port 2 Activate Serial Port 2 I/O Range check Serial Port 2 Base Address MSB Register Serial Port 2 Base Address LSB Register Serial Port 2 Interrupt Level Select Serial Port 2 Interrupt Type Serial Port 2 Special Configuration Register
14
IT8661F
Table 6-5. Parallel Port Configuration Registers LDN*1
03h 03h 03h 03h 03h 03h 03h 03h 03h 03h
Index
30h 31h 60h 61h 62h 63h 70h 71h 74h F0h
R/W
R/W R/W R/W R/W R/W R/W R/W R R/W R/W
Reset
00h 00h 03h 78h 07h 78h 07h 02h 03h 03h*4
Access Mode
ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP MB PnP
Configuration Register or Action
Parallel Port Activate Parallel Port I/O Range Check Parallel Port Base Address 1 MSB Register Parallel Port Base Address 1 LSB Register Parallel Port Base Address 2 MSB Register Parallel Port Base Address 2 LSB Register Parallel Port Interrupt Level Select Parallel Port Interrupt Type Parallel DMA Channel Select*3 Parallel Port Special Configuration Register
Table 6-6. IR Configuration Registers LDN*1
04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h
Index
30h 31h 60h 61h 62h 63h 70h 71h 72h 73h 74h 75h F0h
R/W
R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W
Reset
00h 00h 02h E8h 03h 00h 0Ah 02h 0Bh 02h 01h 00h 00h
Access Mode
ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP ISA PnP ISA PnP/MB PnP ISA PnP/MB PnP MB PnP
Configuration Register or Action
IR Activate IR I/O Range Check IR Base Address 1 MSB Register IR Base Address 1 LSB Register IR Base Address 2 MSB Register IR Base Address 2 LSB Register IR Interrupt Level Select 1 IR Interrupt Type 1 IR Interrupt Level Select 2 IR Interrupt Type 2 IR DMA Channel Select 1 IR DMA Channel Select 2 IR Special Configuration Register
15
IT8661F
Table 6-7. GPIO & Alternate Function Configuration Registers LDN*1
05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h
Index
60h 61h 62h 63h 64h 65h 66h 67h 70h F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Access Mode
MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP MB PnP
Configuration Register or Action
CS0 Base Address MSB Register CS0 Base Address LSB Register CS1 Base Address MSB Register CS1 Base Address LSB Register CS2 Base Address MSB Register CS2 Base Address LSB Register Simple I/O Base Address MSB Register Simple I/O Base Address LSB Register GPIO Interrupt Level Select GPIO[7:0] Pin Polarity Register CS0 Control Register CS1 Control Register CS2 Control Register GPIO[7:0] Function Selection Register Simple I/O[7:0] Direction Selection Register Zero Wait State & High Address Qualification Control Device Zero Wait State Enable Register GPIO[12:8] Pin Polarity Register GPIO[12:8] Function Selection Register Simple I/O[12:8] Direction Selection Register High Address Qualification inputs 1 & 2 Selection High Address Qualification inputs 3 & 4 Selection
Notes: *1: In the ISA PnP mode, the LDNs are dynamic. For example: When the enable register (Index 23h) of a PnP logical device obtains 0Fh (i.e. FDC, Serial Port 1,2 & Parallel Port are enabled); by LDN mapping, 00h stands for FDC; 01h for Serial Port 1; 02h for Serial Port 2; and 03h for Parallel Port. When 06h is given to the register index 23h (only Serial Port 1, 2); by LDN mappings, 00h stands for Serial Port 1, and 01h for Serial Port 2. *2: Both of these two registers can be read from all LDNs but can only be written if LDN=05h. *3: When the ECP mode is not enabled, this register is read-only as "04h", and cannot be written. *4: When the bit 2 of the base address of Parallel Port is set to 1, the EPP mode cannot be enabled. Bit 0 of this register is always 0.
16
IT8661F
6.5.1 Logical Device Base Address The base I/O range of logical devices shown below is stored in the built-in resource data ROM. PnP BIOS or OS will read this data from the resource data ROM to locate the base I/O address range of each logical device. If there are any I/O port conflicts, PnP OS will automatically re-allocate one of the conflicting ports within the base I/O range.
Table 6-8. Base Address of Logical Devices Logical Devices
LDN=0 FDC LDN=1 SERIAL PORT 1
Base I/O Range
[0X0100:0X0FF8] ON 8-BYTE BOUNDARIES [0X0100:0X0FF8] ON 8-BYTE BOUNDARIES
Fixed Base Offsets
+2H : DOR +4H : MSR/DSR +5H : FIFO +7H : DIR/DCR +0H : RBR/TBR/DLL div +1H : IER/DLM div +2H : IIR/FCR +3H : LCR +4H : MCR +5H : LSR +6H : MSR +7H : SCR +0H : RBR/TBR/DLL div +1H : IER/DLM div +2H : IIR/FCR +3H : LCR +4H : MCR +5H : LSR +6H : MSR +7H : SCR +0H : DATA/ecpAfifo +1H : STATUS +2H : CONTROL +3H : EPP address +4H : EPP data 0 +5H : EPP data 1 +6H : EPP data 2 +7H : EPP data 3 +0H : cfifo/ecpDfifo/cnfgA +1H : cnfgB +2H : ecr +3H : Reserved +0H : RBR/TBR/DLL div +1H : IER/DLM div +2H : IIR/FCR +3H : LCR +4H : MCR +5H : LSR +6H : MSR +7H : SCR +0H : MCR +1H : MSR(MISC)/ADDR/Icnfg1 +2H : R(T)fifo/RxBCLR/ITCR +3H : TxC1R/RxBCHR/Icnfg2 +4H : TxC2R/RxRFPLR/TMR +5H : TxSR/RxRFPHR/Icnfg3 +6H : RxC1R/TxBCLR +7H : RxSR(RCR)/TxBCHR
LDN=2 SERIAL PORT 2
[0X0100:0X0FF8] ON 8-BYTE BOUNDARIES
LDN=3 PARALLEL PORT
[0X0100:0X0FF8] ON 8-BYTE BOUNDARIES (SPP : ON 4-BYTE BOUNDARIES) (EPP : ON 8-BYTE BOUNDARIES)
[0X0100:0X0FFC] ON 4-BYTE BOUNDARIES
LDN=4 IR
[0X0100:0X0FF8] ON 8-BYTE BOUNDARIES
[0X0100:0X0FF8] ON 8-BYTE BOUNDARIES
17
IT8661F
6.6 Global Configuration Registers (LDN: All) 6.6.1 Set RD_DATA Port (Index=00h, ISA PnP) Writing to this location modifies the address of the port used for reading from the ISA Plug and Play cards. Bits[7:0] are mapped as bits[9:2] of I/O READ port. The I/O READ port address bits[1:0] contain always "11b". This register is write-only and is only used in the ISA PnP mode. It cannot be written under the MB PnP mode. 6.6.2 Serial Isolation (Index=01h, ISA PnP) A read from this register results in a switch to the "Isolation" state for the Plug and Play card, and then compares with one bit of the card ID. This register is read-only, and used only in the ISA PnP mode. 6.6.3 Configure Control (Index=02h, ISA PnP/MB PnP) This register is write-only. Their values are not sticky; i.e., a hardware reset will clear the bits automatically without the help of software. Bit
7-3 2 Reserved Reset CSN to 0. This bit is only used in the ISA PnP mode, and should not be written with a "1" in the MB PnP mode. Return to the "Wait for Key" state. This bit is used for both the ISA PnP and MB PnP modes when configuration sequence is completed. Reset all logical devices and restore configuration registers to their power-on states. In the ISA PnP mode, writing a "1" to this bit only resets those registers that can be accessed in the ISA PnP mode.
6.6.5 Resource Data (Index=04h, ISA PnP) This register is read-only and used only in the ISA PnP mode. 6.6.6 Status (Index=05h, ISA PnP) Bits[7:1] are reserved. Setting bit 0, it indicates ready to fetch the next data byte from the Resource Data register. 6.6.7 Card Select Number (CSN, Index=06h, Default=00h, ISA PnP) Upon writing to this register, a card's CSN is given. A CSN is a value uniquely assigned to each ISA card after the serial identification process, so that each card may be individually selected during a WAKE[CSN] command. This register is READ/WRITE, and is only used in the ISA PnP mode. 6.6.8 Logical Device Number (LDN, Index=07h, ISA PnP/MB PnP) This register is used to select the current logical devices. By reading from or writing to the configuration of I/O, Interrupt, DMA and other special functions, all registers of the logical device can be accessed. In addition, the I/O RANGE CHECK and ACTIVATE commands are effective only on the selected logical devices. This register is READ/WRITE and used in both the ISA PnP and MB PnP modes. 6.6.9 Chip ID Byte 1 (Index=20h, Default=86h, MB PnP) This register is the Chip ID byte 1 and for read-only. Bits[7:0]=86h when read. 6.6.10 Chip ID Byte 2 (Index=21h, Default=61h, MB PnP) This register is the Chip ID byte 2 and for read-only. Bits[7:0]=61h when read. 6.6.11 Chip Version & Multi-Chips Clarification (Index=22h, Default=00h, MB PnP) This register is the Chip Version. Bits 7,6,3,2,1 are reserved and read-only. Bits 5 and 4 are writeable and used to clarify different systems that use the same IT8661F I/O
Description
1
0
6.6.4 Wake[CSN] (Index=03h, ISA PnP) Writing to this port will assign all cards with a CSN to go from the "Sleep" state to either the "Isolation" state (if data[7:0]=00h) or the "Configuration" state (if data[7:0]=00h), when the CSN matches the write data[7:0]. This register is write-only, and used only in the ISA PnP mode.
18
IT8661F
controller in MB PnP mode. (Refer to the general description of configuring sequence.). If the IT8661F chip is implemented, the configuring sequence is not affected by these two bits. Bit 0 is read only and represents the chip version, as IT8661F if set to "0". 6.6.12 PnP Logical Device Enable Register (Index=23h, Default=00h, MB PnP) The logical devices will not be involved in the ISA PnP protocol sequence except when the enable bits of the PnP logical devices are set. Bit
7-5 4 3 2 1 0 Reserved IR Parallel Port Serial Port 2 Serial Port 1 FDC
Bit
7-2 1 0 Reserved
Description
Input Clock Select 1 : 48MHz 0 : 24MHz SOFTWARE SUSPEND 1 : Suspend 0 : Normal
6.6.14 GPIO Function Enable Registers[12:8] (Index=25h, Default=00h, MB PnP) The bits[4:0] are mapped as the GPIO Function Enable Register[12:8]. The enable bits should be set to "1" to enable the GPIO function, otherwise, the multi-function pins will perform the original functions. Bits[7:5] are reserved. This register can be read from any LDN but can only be written if LDN=05h. Bit
7-5 4 3 2 1 0 Reserved Enable GPIO Function 12 (pin 26) Enable GPIO Function 11 (pin 25) Enable GPIO Function 10 (pin 19) Enable GPIO Function 9 (pin 98) Enable GPIO Function 8 (pin 94)
Description
Description
In the ISA PnP mode, the LDNs are dynamic. The default sequence is FDC, Serial Port 1, Serial Port 2, Parallel Port and IR. If one of the bits is not set, the corresponding LDNs of the devices after this current one are subtracted by one. For example: when 0Fh is given to bits[7:0] (PnP logical device enable: FDC, Serial Port 1, 2 & Parallel Port). By LDN mapping, we will get 00h as FDC, 01h as Serial Port 1, 02h as Serial Port 2, and 03h as Parallel Port. When 06h is given to bits[7:0] (only Serial Port 1, 2). By LDN mapping, we will get 00h as Serial Port 1, and 01h as Serial Port 2. 6.6.13 Software Suspend and Input Clock Select (Index=24h, Default=00h, MB PnP) Bit 0 is the SOFTWARE SUSPEND. When bit 0 is set to "1", the IT8661F is in the "SOFTWARE SUSPEND" state. All the devices remain inactive until this bit is cleared or the WAKE-UP event occurs. The WAKEUP event occurs at any transition on signals RI1 (pin 84) and RI2 (pin 86). Bit 1 is for the input clock selection. When this bit is set to "0", the input clock of the IT8661F is 24MHz. When set to "1", the input clock is 48MHz.
6.6.15 GPIO Function Pin Enable Register[7:0] (Index=26h, Default=00h, MB PnP) This register is GPIO Function Enable Register[7:0]. The enable bits should be set to enable the GPIO function, otherwise, the multi-function pins will perform the original functions. This register can be read from any LDN, but can only be written if LDN=05h. Bit
7 6 5 4 3 2 1 0
Description
Enable GPIO Function 7 (pin 93) Enable GPIO Function 6 (pin 92) Enable GPIO Function 5 (pin 91) Enable GPIO Function 4 (pin 90) Enable GPIO Function 3 (pin 89) Enable GPIO Function 2 (pin 88) Enable GPIO Function 1 (pin 87) Enable GPIO Function 0 (pin 86)
19
IT8661F
6.7 FDC Configuration Registers (LDN=00h) 6.7.1 FDC Activate (Index=30h, Default=00h, ISA PnP/MB PnP) Bit
7-1 0 Reserved FDC Enable 1: enable 0: disable This is a READ/WRITE register. I/O Range Check must be disabled before it is to be set active. 2-0
6.7.4 FDC Base Address LSB Register (Index=61h, Default=F0h, ISA PnP/MB PnP) Bit Description
READ/WRITE, mapped as Base Address[7:3] Read-only as "000b"
Description
7-3
6.7.5 FDC Interrupt Level Select (Index=70h, Default=06h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Reserved with default "0h" Select the interrupt level for FDC Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid 0h : no interrupt selected
6.7.2 FDC I/O Range Check (Index=31h, Default=00h, ISA PnP) This register is used, in the ISA PnP mode, to perform a conflict check on the I/O port range programmed for FDC. Bit
7-2 1 Reserved Enable I/O Range Check. If set, then I/O Range Check is enabled. Before set, FDC should be inactive. If set, the IT8661F is forced to respond with a "55h" to I/O READ of the assigned I/O range of FDC when I/O Range Check is in operation. If cleared, it then sends an "AAh" in response.
Description
6.7.6 FDC Interrupt Type (Index=71h, Default=02h, ISA PnP) This register indicates the type of interrupt used for FDC, and is read-only as default "02h" (to indicate the traditional interrupt type, edge trigger). 6.7.7 FDC DMA Channel Select (Index=74h, Default=02h, ISA PnP/MB PnP) Bit
7-3 2-0
0
6.7.3 FDC Base Address MSB Register (Index=60h, Default=03h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Reserved with default "00h" Select the DMA channel for FDC 7h-5h : not valid 4h : no DMA channel selected 3h : DMA3 2h : DMA2 1h : DMA1 0h : DMA0
Description
Read-only, with "0h" for Base Address[15:12] Mapped as Base Address[11:8]
20
IT8661F
6.7.8 FDC Special Configuration Register (Index=F0h, Default=00h, MB PnP) Bit
7-4 3 2 1 0
6.8.3 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Reserved with default "00h" 1 : IRQ sharing 0 : Normal IRQ 1 : Swap Floppy Drives A, B 0 : Normal 1 : 3-mode 0 : AT mode 1 : Software Write Protect 0 : Normal
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
6.8.4 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h, ISA PnP/MB PnP) Bit
7-3 2-0
Description
READ/WRITE, mapped as Base Address[7:3] Read-only as "000b"
6.8 Serial Port 1 Configuration Registers (LDN=01h) 6.8.1 Serial Port 1 Activate (Index=30h, Default=00h, ISA PnP/MB PnP) Bit
7-1 0 Reserved Serial Port 1 Enable 1: enable 0: disable This is a READ/WRITE register. I/O Range Check must be disabled before it is to be set active.
6.8.5 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h, ISA PnP/MB PnP) Bit 7-4 3-0 Description
Reserved with default "0h" Select the interrupt level for Serial Port 1 Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid 0h : no interrupt selected
Description
6.8.2 Serial Port 1 I/O Range Check (Index=31h, Default=00h, ISA PnP) This register is used, in the ISA PnP mode, to perform a conflict check on the I/O port range programmed for Serial Port 1. Bit
7-2 1
6.8.6 Serial Port 1 Interrupt Type (Index=71h, Default=02h, ISA PnP) This register indicates the type of interrupt used for Serial Port 1, and is read-only as 02h (to indicate the traditional interrupt type, edge trigger). 6.8.7 Serial Port 1 Special Configuration Register (Index=F0h, Default=00h, MB PnP) Bit
7-2 1
Description
Reserved with default "00h" I/O Range Check 1 : enable 0 : disable Serial Port 1 must be inactive before it is to be set.
0
If set, the IT8661F is forced to respond a "55h" to I/O READ of the assigned I/O range of Serial Port 1 when I/O Range Check is in operation. If cleared, it then sends an "AAh" in response.
Description
Reserved with default "00h" 1 : IRQ sharing 0 : normal
0
1 : MIDI support enabled 0 : MIDI support disabled
21
IT8661F
6.9 Serial Port 2 Configuration Registers (LDN=02h) 6.9.1 Serial Port 2 Activate (Index=30h, Default=00h, ISA PnP/MB PnP) Bit
7-1 0 Reserved Serial Port 2 Enable 1: enable 0: disable This is a READ/WRITE register. I/O Range Check must be disabled before it is to be set active.
6.9.4 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h, ISA PnP/MB PnP) Bit
7-3 2-0
Description
READ/WRITE, mapped as Base Address[7:3] Read-only as "000b"
Description
6.9.5 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Reserved with default "0h" Select the interrupt level for Serial Port 2 Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid 0h : no interrupt selected
6.9.2 Serial Port 2 I/O Range Check (Index=31h, Default=00h, ISA PnP) This register is used, in the ISA PnP mode, to perform a conflict check on the I/O port range programmed for Serial Port 2. Bit
7-2 1
Description
Reserved with default "00h" I/O Range Check 1 : enable 0 : disable Before set, Serial Port 2 should be inactive.
6.9.6 Serial Port 2 Interrupt Type (Index=71h, Default=02h, ISA PnP) This register indicates the type of interrupt used for Serial Port 2, and is read-only as "02h" (to indicate the traditional interrupt type, edge trigger). 6.9.7 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h, MB PnP) Bit
7-2 1 0
0
If set, the IT8661F is forced to respond a "55h" to I/O READ of the assigned I/O range of Serial Port 2 when I/O Range Check is in operation. If cleared, it then sends an "AAh" in response.
6.9.3 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Reserved with default "00h" 1 : IRQ sharing 0 : normal 1 : MIDI support enabled 0 : MIDI support disabled
Description
Read-only with "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
22
IT8661F
6.10 Parallel Port Configuration Registers (LDN=03h) 6.10.1 Parallel Port Activate (Index=30h, Default=00h, ISA PnP/MB PnP) Bit
7-1 0 Reserved Parallel Port Enable 1: enable 0: disable This is a READ/WRITE register. I/O Range Check must be disabled before it is to be set active.
6.10.5 Parallel Port Base Address 2 MSB Register (Index=62h, Default=07h, ISA PnP/MB PnP) This register is used only when the ECP mode is enabled. Bit
7-4 3-0
Description
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
6.10.2 Parallel Port I/O Range Check (Index=31h, Default=00h, ISA PnP) This register is used, in the ISA PnP mode, to perform a conflict check on the I/O port range programmed for Parallel Port. Bit
7-2 1 Reserved I/O Range Check 1 : enable 0 : disable Parallel Port must be inactive before it is to be set. 0 If set, the IT8661F is forced to respond with a "55h" to I/O READ of the assigned I/O range of Parallel Port when I/O Range Check is in operation. If cleared, it then sends an "AAh" in response.
6.10.6 Parallel Port Base Address 2 LSB Register (Index=63h, Default=78h, ISA PnP/MB PnP) This register is used only when the ECP mode is enabled. Bit
7-2 1-0
Description
READ/WRITE, mapped as Base Address[7:2] Read-only as "00b"
Description
6.10.7 Parallel Port Interrupt Level Select (Index=70h, Default=07h, ISA PnP/MB PnP) Bit Description
7-4 Reserved with default "0h" 3-0 Select the interrupt level for Parallel Port Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid 0h : no interrupt selected
6.10.3 Parallel Port Base Address 1 MSB Register (Index=60h, Default=03h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
6.10.8 Parallel Port Interrupt Type (Index=71h, Default=02h, ISA PnP) This register indicates the type of interrupt used for the Parallel Port, and is read-only as "02h" (to indicate the traditional interrupt type, edge trigger).
6.10.4 Parallel Port Base Address 1 LSB Register (Index=61h, Default=78h, ISA PnP/MB PnP) Bit
7-2 1-0
Description
READ/WRITE, mapped as Base Address[7:2] Read-only as "00b"
23
IT8661F
6.10.9 Parallel Port DMA Channel Select (Index=74h, Default=03h, ISA PnP/MB PnP) Bit
7-3 2-0
6.11.2 IR I/O Range Check (Index=31h, Default=00h, ISA PnP) This register is used, in the ISA PnP mode, to perform a conflict check on the I/O port range programmed for IR. Bit
7-2 1 Reserved Enable I/O Range Check. If set, then I/O Range Check is enabled. Before set, IR should be inactive. If set, the IT8661F is forced to respond with a "55h" to I/O READ of the assigned I/O range of IR when I/O Range Check is in operation. If cleared, it then sends an "AAh" in response.
Description
Reserved with default "00h" Select the DMA channel for Parallel Port 7h-5h : not valid 4h : no DMA channel selected 3h : DMA3 2h : DMA2 1h : DMA1 0h : DMA0
Description
0
6.10.10 Parallel Port Special Configuration Register (Index=F0h, Default=03h, MB PnP) Bit
7-3 2
Description
Reserved with default "00h" This bit is used to program the IRQ sharing function 1 : IRQ sharing enabled 0 : Normal IRQ output Parallel Port mode 00 : Standard Parallel Port mode (SPP) 01 : EPP mode 10 : ECP mode 11 : EPP mode & ECP mode
6.11.3 IR Base Address 1 MSB Register (Index=60h, Default=02h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Read-only as "0h" for Base Address[15:12] Mapped as Base Address[11:8]
1-0
6.11.4 IR Base Address 1 LSB Register (Index=61h, Default=E8h, ISA PnP/MB PnP) Bit
7-3 2-0
If bit 1 is set, ECP mode is enabled. If bit 0 is set, EPP mode is enabled. These two bits are independent. However, according to the EPP specification, the EPP mode cannot be enabled when bit 2 of the Parallel Port Base Address 1 LSB (index 61h) is set to "1". 6.11 IR Configuration Registers (LDN=04h) 6.11.1 IR Activate (Index=30h, Default=00h, ISA PnP/MB PnP) Bit
7-1 0 Reserved IR Enable 1: enable 0: disable This is a READ/WRITE register. I/O Range Check must be disabled before it is to be set active.
Description
READ/WRITE, mapped as Base Address[7:3] Read-only as "000b"
6.11.5 IR Base Address 2 MSB Register (Index=62h, Default=03h, ISA PnP/MB PnP) Bit
7-4 3-0
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
Description
24
IT8661F
6.11.6 IR Base Address 2 LSB Register (Index=63h, Default=00h, ISA PnP/MB PnP) Bit
7-3 2-0
6.11.10
IR Interrupt Type 2 (Index=73h, Default=02h, ISA PnP)
Description
READ/WRITE, mapped as Base Address[7:3] Read-only as "000b"
This register indicates the type of interrupt used for IR, and is read-only as "02h" (to indicate the traditional interrupt type, edge trigger). 6.11.11 IR DMA Channel Select 1 (Index=74h, Default=01h, ISA PnP/MB PnP) Bit
7-3 2-0
6.11.7 IR Interrupt Level Select 1 (Index=70h, Default=0Ah, ISA PnP/MB PnP) Bit Description
Description
Reserved with default "00h" Select the DMA channel for IR Port 7h-5h : not valid 4h : no DMA channel selected 3h : DMA3 2h : DMA2 1h : DMA1 0h : DMA0
7-4 Reserved with default "0h" 3-0 Select the interrupt level for IR Port Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid 0h : no interrupt selected
6.11.12 IR DMA Channel Select 2 (Index=75h, Default=00h, ISA PnP/MB PnP) Bit Description
Reserved with default "00h" Select the DMA channel for IR Port 7h-5h : not valid 4h : no DMA channel selected 3h : DMA3 2h : DMA2 1h : DMA1 0h : DMA0
6.11.8 IR Interrupt Type 1 (Index=71h, Default=02h, ISA PnP) This register indicates the type of interrupt used for IR, and is read-only as "02h" (to indicate the traditional interrupt type, edge trigger). 6.11.9 IR Interrupt Level Select 2 (Index=72h, Default=0Bh, ISA PnP/MB PnP) Bit Description
7-3 2-0
7-4 Reserved with default "0h" 3-0 Select the interrupt level for IR Port Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid 0h : no interrupt selected
25
IT8661F
6.11.13 IR Special Configuration Register (Index=F0h, Default=00h, MB PnP) Bit
7-6 5 Reserved This bit is used to program the IRQ sharing function 1 : IRQ sharing enabled 0 : Normal IRQ output SIR Mode Select 1: ASKIR 0: HPSIR 1 : Half Duplex for SIR or ASKIR 0 : Full Duplex for SIR or ASKIR 1: Dual DMA Channel One DMA channel is for transmitting and the other one is for receiving. 0: Single DMA Channel This DMA channel is for both transmitting and receiving. 1: Dual Interrupt Level One interrupt level is for FIR mode and the other one is for MIR mode. 0: Single Interrupt Level This interrupt level is for both FIR and MIR modes. FIR Transceiver Mode Select 1 : 2 Input Transceiver (HP-Like) 0 : 1 Input Transceiver (IBM-Like)
6.12.2 CS0 Base Address LSB Register (Index=61h, Default=00h, MB PnP) Bit
7-0
Description
Description
READ/WRITE, mapped as Base Address[7:0]
6.12.3 CS1 Base Address MSB Register (Index=62h, Default=00h, MB PnP) Bit
7-4 3-0
4
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
3 2
6.12.4 CS1 Base Address LSB Register (Index=63h, Default=00h, MB PnP) Bit
7-0
Description
READ/WRITE, mapped as Base Address[7:0]
1
6.12.5 CS2 Base Address MSB Register (Index=64h, Default=00h, MB PnP) Bit
7-4 3-0
0
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
6.12 GPIO & Alternate Function Configuration Registers (LDN=05h) 6.12.1 CS0 Base Address MSB Register (Index=60h, Default=00h, MB PnP) Bit
7-4 3-0
6.12.6 CS2 Base Address LSB Register (Index=65h, Default=00h, MB PnP) Bit
7-0
Description
READ/WRITE, mapped as Base Address[7:0]
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
26
IT8661F
6.12.7 Simple I/O Base Address MSB Register (Index=66h, Default=00h, MB PnP) Bit
7-4 3-0
6.12.11 CS0/CS1/CS2 Control Register (Index=F1h/F2h/F3h, Default=00h, MB PnP) Bit
7-6
Description
Read-only as "0h" for Base Address[15:12] READ/WRITE, mapped as Base Address[11:8]
Description
Base Address Alignment 00 : single port 01 : 2 ports 10 : 4 ports 11 : 8 ports Chip Select Type 00 : Pure Address Decode 01 : Address Decode and IOR command 10 : Address Decode and IOW command 11 : Address Decode and (IOR or IOW command) See Locationnote on page 29.
6.12.8 Simple I/O Base Address LSB Register (Index=67h, Default=00h, MB PnP) Bit
7-0
5-4
Description
READ/WRITE, mapped as Base Address[7:0]
6.12.9 GPIO Interrupt Level Select (Index=70h, Default=00h, MB PnP) This register is used to program the pin type as either a simple inverting or non-inverting for GPIO [7:0]. Bit
7-4 3-0
3-0
6.12.12 GPIO[7:0] Function Selection Register (Index=F4h, Default=00h, MB PnP) This register is used to select the function to be either the Simple I/O or the Alternate function. Bit
7-0 For each bit 1 : Simple I/O 0 : Alternate function
Description
See Pin Locationnote on page 29. Select the interrupt level for GPIO Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid 0h : no interrupt selected
Description
6.12.13 Simple I/O[7:0] Direction Selection Register (Index=F5h, Default=00h, MB PnP) This register is used to determine the direction of the Simple I/O. Bit
7-0 For each bit 1 : Input mode 0 : Output mode
6.12.10 GPIO[7:0] Pin Polarity Register (Index=F0h, Default=00h, MB PnP) Bit
7-0 For each bit 1 : inverting 0 : non-inverting
Description
Description
27
IT8661F
6.12.14 Zero Wait State Control & On-Chip High Address Qualification Enable Register (Index=F6h, Default=00h, MB PnP) Bit
7-6 5 Reserved This bit is used to program the IRQ sharing function 1 : IRQ sharing enabled 0 : Normal IRQ output This bit is used to enable or disable the GPIO pin to be as high address SA[15:12] input pin for 16-bit address decoding 0 : disable on-chip high address qualification 1 : enable on-chip high address qualification See Locationnote of Zero Wait State function on page 29.
6.12.16 GPIO[12:8] Pin Polarity Register (Index=F8h, Default=00h, MB PnP) This register is used to program the GPIO[12:8] pin type as polarity inverting or non-inverting for GPIO[12:8]. Bit
7-5 4-0 Reserved For each bit 1 : inverting 0 : non-inverting
Description
Description
4
6.12.17 GPIO[12:8] Function Selection Register (Index=F9h, Default=00h, MB PnP) This register is used to select the function as to be either the Simple I/O or Alternate function. Bit
7-5 4-0 Reserved For GPIO[12:8] 1 : Simple I/O 0 : Alternate function
3-0
Description
6.12.15 Device Zero Wait State Enable Register (Index=F7h, Default=00h, MB PnP) This register is used to determine which device is enabled in the ZWS function. The bits should be set to "1" to enable the ZWS function. Bit
7 6 5 4 3 2 1 0 Reserved Reserved EPP Port (Parallel Port Base Address + 3h~7h) SPP & ECP Port Serial Port 2 Serial Port 1 FDC
6.12.18 Simple I/O[12:8] Direction Selection Register (Index=FAh, Default=00h, MB PnP) This register is used to determine the direction of the Simple I/O[12:8]. Bit
7-5 4-0 Reserved For each bit 1 : Input mode 0 : Output mode
Description
GPIO (Simple I/O, CS0, CS1, CS2)
Description
28
IT8661F
6.12.19 High Address Qualification Inputs 1 & 2 Selection Register (Index=FBh, Default = 00h, MB PnP) This register is used to program the Pin location of high address inputs 1 and 2 for 16bit address decoding. Bit
7-4 3-0
Description
See Locationnote of high address input 2 below. See Locationnote of high address input 1 below.
6.12.20 High Address Qualification Inputs 3 & 4 Selection Register (Index=FCh, Default = 00h, MB PnP) This register is used to program the Pin location of high address inputs 3 and 4 for 16bit address decoding. Bit
7-4 3-0
Description
See Locationnote of high address input 4 below. See Locationnote of high address input 3 below.
Note: The Location mapping
Location
0000 0010 0100 0110 1000 1010 0001 0011 0101 0111 1001 1011 1101 1111 else
Description
None GPIO 8 (pin 94) GPIO 9 (pin 98) GPIO 10 (pin 19) GPIO 11 (pin 25) GPIO 12 (pin 26) GPIO 0 (pin 86) GPIO 1 (pin 87) GPIO 2 (pin 88) GPIO 3 (pin 89) GPIO 4 (pin 90) GPIO 5 (pin 91) GPIO 6 (pin 92) GPIO 7 (pin 93) Reserved
29
IT8661F
7. Functional Description
7.1 General Purpose I/O The IT8661F provides a set of flexible I/O control and special functions for system designers through a set of General Purpose I/O pins (GPIO). All thirteen GPIO pins are multi-function pins. They will not perform GPIO functions unless the bits of the GPIO function pin enable registers (Index 25h & 26h of Global Configuration Register) are set. GPIO functions include the Simple I/O function and the Alternate function. The Simple I/O function includes a set of registers, which corresponds to the GPIO pins. All control bits are divided into two registers (Simple I/O 1, GPIO[7:0]; Simple I/O 2, GPIO[12:8]). The accessed I/O ports are programmable and are two consecutive I/O ports (Base Address & Base Address+1). Base Address is programmed on the registers of GPIO Alternate Function (LDN=05h, Index=66h & 67h). The Alternate Function provides several special functions for use, including three chip select strobes (CS0, CS1, CS2), Zero Wait State, Interrupt level mapping, and On-chip High Address SA[15:12] Qualification. All functions can be programmed to all thirteen GPIO pins. There are three registers that should be programmed to enable an alternate function, Index 26h (or 25h) and F4h (or F9h) or LDN 05h and pin location bits of each Alternate function. In IT8661F, there are flexible control register related to each of the three chip select strobes (Index F1h, F2h, F3h, LDN 05h). Each can be programmed as 1 or 2 or 4 or 8 by consecutive I/O port decoding. It can also be programmed to qualify with IOR# and IOW# states. There are four types of qualifying conditions: pure address decided, asserted on address matching and IOR# asserted, asserted on address matching and IOW# asserted, asserted on address matching and IOR# or IOW# asserted. The Zero Wait State function is used to reduce the cycle time of the ISA bus when the IT8661F is accessed. The IT8661F provides a set of enable registers for the logical devices that are activated with Zero Wait State function when they are accessed. By programming this register, users can select the logical devices which are fast enough to set the Zero Wait State of the ISA bus. The Interrupt level mapping function provides a useful feature for the motherboard designer. Through this mapping, the interrupt level of other on-board devices can be easily changed by software. The programming method is to set the related bits on the registers Index 26h (or 25h), F4h (or F9h) and F5h (or FAh). The pin location mapping, Index 70h must be also programmed correctly. The on-chip high address SA[15:12] qualification for 16-bit address decoding function provides a useful feature for the system designer to design full 16-bit address decoding without any additional TTL. The programming method is to set the related bits on register index 26h (or 25h), F4h (or F9h) and bit 4 of index F6h to enable this function. Index FBh and FCh are used to determine the pin location of these four input high addresses.
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IT8661F
1 IDX F6h 2 IDX F1h 3 IDX F2h 4 IDX F3h IDX F4h (or F9h)
0
ZWS CS0 CS1 CS2 SD-bus WR_
D-FF IDX F5h (or FAh)
1 2 3 4
IDX F0h (or F8h)
1
0 1
RD_
Simple I/O Register IDX 70h GP Interrupt Bit-n
5 6 7 8
GP I/O PIN High Address 1 5,6 IDX FBh High Address 2 High Address 3 7,8 IDX FCh High Address 4
Note: All GPIO pins are internally pulled up 50 K except GPIO10 (pin 19).
Figure 7-1. General Logic of GPIO Function
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IT8661F
7.2 FDC Register Description 7.2.1 Digital Output Register (DOR) - (Base Address + 02h) This register controls drive selection and drive motor. The I/O interface reset may be used at any time to clear DOR's contents. Table 7-1. Digital Output Register (DOR) Bit
7 6 5 4 3 2 1 0
Symbol
MOTB EN MOTA EN DMAEN RESET# DVSEL Reserved Reserved
Description
Drive B Motor Enable bit, active high Drive A Motor Enable bit, active high Disk Interrupt and DMA Enable bit, active high FDC Function Reset bit, active low. This reset doesn't affect DSR, CCR and DOR. Reserved Drive Selection. When it is low, select drive A. When it is high, select drive B
7.2.2 Main Status Register (MSR) - (Base Address + 04h) This register indicates the disk controller status. It should be read before each byte is sent to or received from the data register, except when in DMA mode. Table 7-2. Main Status Register (MSR) Bit
7 6
Symbol
RQM DIO
Description
Request for Master When this bit is set high, the host can transfer data. Data Input/Output bit Indicates the direction of data transfer once a RQM is set. Logic 1 = READ. Logic 0 = WRITE. Non-DMA Mode Active high. This bit is used with the SPECIFY command. Diskette Control Busy Is set active (high) during the execution of a command, and inactive (low) at the end of the result phase. Reserved Reserved Drive B Busy Is set high when drive B is in the SEEK portion of a command. Drive A Busy It is set high when drive A is in the SEEK portion of a command.
5 4
NDM CB
3 2 1
DBB
0
DAB
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IT8661F
7.2.3 Data Register (FIFO) - (Base Address + 05h) This 8-bit data register actually consists of several registers in a stack, and only one register is presented to the data bus at a time when storing data commands and parameters, or providing diskette-drive status information.
7.2.4 Digital Input Register (DIR) - (Base + 07h) Table 7-3. Digital Input Register (DIR) Bit
7
Symbol
DSKCHG
Description
Diskette Change bit Indicates the inverting value of which is monitored from the input of the Diskette Change pin (DSKCHG#) Undefined, high-impedance while being read
6-0
7.2.5 Diskette Control Register (DCR) - (Base Address + 07h WRITE) The transfer rate register is a 2-bit, read-only register which controls a programmable divider and provides 16/ 8/ 4.8/ 4 MHz clocks for four different data transfer rates. The bits are defined below: Table 7-4. Diskette Control Register (DCR) Bit 0
0 1 0 1
Bit 1
0 0 1 1
Transfer Rates
500K bps 300K bps 250K bps 1M bps
Clock Rates
8 MHz 4.8 MHz 4 MHz 16 MHz
Reduce Write
0 1 1 1
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IT8661F
7.2.6 Status Register These 4-byte read-only registers indicate the status of some determined commands that have been executed during their result phase. Their contents are described in the tables below: Table 7-5. Status Register 0 Bit
7, 6
Symbol
IC
Name
Interrupt Code
Description
00 - Execution of the command is completed and correct 01 - Execution of the command was begun, but not successfully completed 10 - INVALID command 11 - The execution of the command is not correctly completed, caused by polling The FDC executes a SEEK, RELATIVE SEEK or RE-CALIBRATE command. The TRK00# pin cannot be active after a RE-CALIBRATE command is issued, or when the FDC steps outward beyond track 0 with a relative command. Not Ready The current head address Select drive B Select drive A
5 4
SE EC
Seek End Equipment Check
3 2 1 0
NR H DSB DSA
Not Ready Head Address Drive B Select Drive A Select
Table 7-6. Status Register 1 Bit
7
Symbol
EN
Name
End of Cylinder
Description
FDC attempts to access a sector beyond the final sector of the track. If TC is not issued after READ or WRITE DATA commands, it will be set. Unused, always 0 A CRC error occurs in the ID field or the data field is detected by FDC. Overrun on a READ operation or Underrun on a WRITE operation is caused by an insufficient time interval for the CPU or DMA to service the FDC. This bit is always "0." 1. FDC cannot find the indicated sector during the READ DATA or READ DELETED DATA commands. 2. While executing a READ ID command, an error occurs upon reading the ID field. 3. While executing a READ TRACK command, the FDC cannot find the starting sector. Activated when a WRITE or FORMAT Command is being executed on a WRITE-protected diskette. 1. The FDC cannot find a data address mark on the specified track or Deleted Data Address mark. 2. The FDC cannot find any ID address on the specified track after two index pulses are detected from the INDEX # pin.
6 5 4
DE OR
Data Error Overrun/ Underrun
3 2
ND No Data
-
1 0
NW MA
Not Writeable Missing Address Mark
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IT8661F
Table 7-7. Status Register 2 Bit
7 6 5 4 3 2 1 0
Symbol
CM DD WC SH SN BC MD
Name
Control Mark Data Error in Data Field Wrong Cylinder Scan Equal Hit Scan Not Satisfied Bad Cylinder Missing Data Address Mark
Description
Unused, this bit is always "0." When the FDC finds a Delete Data Address mark with a READ DATA or SCAN command, this flag bit is set. When a CRC error is found in the data field, this flag bit is set. The track address in the ID field is different from the track address specified in the FDC. When the condition of "equal" is satisfied with a SCAN command, this flag bit is set. When FDC cannot find a sector on the cylinder with a SCAN command, this flag bit is set. The track address FFh is different from the track address in the FDC. The Data Address Mark or Deleted Data Address Mark cannot be found by FDC.
Table 7-8. Status Register 3 Bit
7 6 5 4 3 2 1 0
Symbol
FT WP RDY TK0 TS HD US1 US0 Fault
Name
Write Protect Ready Track 0 Two Side Head Address
Description
The status of the Fault signal from the FDD The status of the Write Protected signal from the FDD The status of the Ready signal from the FDD The status of the Track 0 signal from the FDD The status of the Two Side signal from the FDD The status of the Side Select signal to the FDD
Unit Select. Indicates the current status of the Unit Select signals to FDD.
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IT8661F
7.2.7 Reset The IT8661F implements two types of reset on FDC: software and hardware. Either will perform FDC RESET, releasing the FDC to idle state. Attempting a RESET while writing to the disk will cause corruption of data and CRC. (1) Hardware Reset (Reset Pin) With this RESET, all registers of the FDC CORE are cleared (except those programmed by the SPECIFY Command). To exit the RESET state, the DOR bit must be cleared by the host. (2) Software Reset (DOR reset and DSR reset) The difference between DOR and DSR is that DSR is self-clearing, while DOR must be cleared by the host in order to exit the RESET state. The DOR reset has higher priority than the DSR RESET. 7.2.8 Controller Phases There are three controller phases in the FDC: Command phase, Execution phase, and Result phase. (1) Command Phase When FDC accepts a command from the host before this phase finishes, a set of commandcode bytes and parameter bytes have to be given in the order that the FDC requires. The FDC READ step is enabled only if MSR(7)=1 and MSR(6)=0 (RQM and DIO bit). RQM is set false after each byte-READ cycle, and set true again when a new parameter byte is required, continuing in the READ state while the READ step remains 0. (2) Execution Phase This phase can be completed by the SPECIFY command in DMA or NON-DMA modes. By using the CONFIGURE command, FIFO can automatically be enabled and disabled after each RESET. (3) Result Phase This phase begins when the IRQx pin is activated. The defined set of result bytes must be read by the Host before this phase can be completed. Before the FDC starts to read data, RQM and DIO must be set high. When the READ step ends, RQM=1, DIO=0, and CB bit is cleared. 7.2.9 Data Transfer Commands Description All DATA TRANSFER commands utilize the same parameter bytes and return the same result data byte, differentiating between them only in the five bits (0~4) of the first byte. By sending a CONFIGURE Command, the user transparent implied seek can be enabled. During execution of the SEEK, the Drive Busy bit in MSR is active; if the SEEK fails, the Status Register 0 will contain the error code and the current cylinder will be indicated by the symbol C.
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IT8661F
Table 7-9. Command Symbol Description Symbol
A0 C D D7 - D0 DTL EOT GPL
Name
Address Line 0 Cylinder Number Data Data Bus Data Length End of Track Gap Length
Description
A0 controls selection of Main Status Register (A0 =0) or Data Register (A0 =1). C stands for the current/selected cylinder (track) number 0 through 76 or the medium. D stands for the data pattern which is going to be written into a sector. 8-bit Data Bus, where D7 stands for the most significant bit, and D0 stands for the least significant bit. When N is defined as 00, DTL stands for the data length which users are going to read out or write into the sector. EOT stands for the final sector number on a cylinder. During a READ or WRITE operation FDC will stop data transfer after a sector # equal to EOT. GPL stands for the length of Gap 3. During READ/WRITE commands, this value determines the number of bytes that VCOs will stay low after two CRC bytes. During the FORMAT command it determines the size of Gap 3. H stands for Head number 0 or 1, as specified in ID field. HD stands for a selected Head number 0 or 1 and controls the polarity of pin 27. (H = HD in all command words.) HLT stands for the Head Load Time in the FDD (2 to 254 ms in 2 ms increments). HUT stands for the Head Unload Time after a READ or WRITE operation has occurred (16 to 240 ms in 16 ms increments). If MF is low, FM mode is selected, and if it is high, MFM mode is selected. If MT is high, a multi-track operation is to be performed. If MT=1 after finishing READ/WRITE operation on side 0, FDC will automatically start searching for sector one on side one. N stands for the number of data bytes written in sector. NCN stands for a new cylinder number, which is going to be reached as a result of the SEEK operation. Desired position of Head. ND stands for operation in the Non-DMA Mode. PCN stands for the cylinder number at the completion of SENSE INTERRUPT STATUS Command. Position of Head at present time. R stands for the sector number, which will be read or written. R/W stands for either READ (R) or WRITE (W) signal. SC indicates the number of sectors per cylinder. SK stands for Skip Deleted Data Address Mark. SRT stands for the Stepping Rate for the FDD. (1 to 16 ms in 1 ms increments.) Stepping Rate applies to all drives. (F=1 ms, E=2 ms, etc.)
H HD HLT HUT MF MT
Head Address Head Head Load Time Head Unload Time FM or MFM Mode Multi-Track
N NCN ND PCN R R/W SC SK SRT
Number New Cylinder Number Non-DMA Mode Present Cylinder Number Record READ/WRITE Sector Skip Step Rate Time
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IT8661F
Table 7-9. Command Symbol Description (cont'd) Symbol
ST0 ST1 ST2 ST3
Name
Status 0 Status 1 Status 2 Status 3
Description
ST 0-3 stands for one of four registers which stores the status information after a command has been executed. This information is available during the result phase after command execution. These registers should not be confused with the main status register (selected by A0 = 0); ST 0-3 may be read only after a command has been executed and contains information relevant to that particular command. During a SCAN operation, if STP = 1, the data in contiguous sectors is compared byte by byte with data sent from the processor (or DMA); and if STP = 2, then alternate sectors are read and compared.
STP US0, US1 Unit Select
US stands for a selected drive number 0 or 1.
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IT8661F
(1) READ DATA This mode is set by nine command bytes. Each READ operation is initialized by a READ command and finished by reading the data from FIFO through FDC. The sector address automatically increases by 1 and the data from the next sector is read and sent through the FIFO. This continuous function is called a "Multi Sector READ Operation". When a TC or an implied TC is received, the FDC stops sending data, but continues to read data from the current sector. In addition, it checks the CRC bytes until the READ operation is completed to the end of the sector. The sector size is determined by the N value, from the following formula : sector size = 2(7+N value) bytes. If the sector size is 128 and the DTL is less, the remaining bytes will be read and checked for CRC error by the FDC. If this occurs in a WRITE operation, the remaining bytes will be filled with 0. If the sector size is not 128, (N > 00), the DTL should be set to FFh. The MT (multi-track) allows the FDC to read both sides of the diskette. Both N and MT determine the amount of data, as indicated in table below:
Table 7-10. Effects of MT and N Bits
MT 0 1 0 1 0 1 N 1 1 2 2 3 3 Maximum Transfer Capacity 256 X 26 = 6656 256 X 52 = 13312 512 X 15 = 7680 512 X 30 = 15360 1024 X 8 = 8192 1024 X16 =16384 Final Sector Read from Disk 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1
Table 7-11. Description of the READ DATA Command
Phase
Command
R/W
W W W W W W W W W
D7
D6
D5
Data Bus D4 D3
D2
D1
D0
Remarks
Command Codes Sector ID information before the command execution
MT MFM SK 0 0 1 1 0 0 0 0 0 0 HDS DS1 DS0 ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________ ___________________________ EOT_____________________________ ___________________________ GPL_____________________________ ___________________________ DTL_____________________________
Execution Result R R R R R R R
Data transfer between the FDD and the main system. ___________________________ ST0_____________________________ ___________________________ ST1_____________________________ ___________________________ ST2_____________________________ ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________ Sector ID information after command execution. Status information after command execution
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IT8661F
(2) READ DELETED DATA The READ DELETED DATA command is identical to the READ DATA provided in the previous section except for operation on sectors which have a Deleted Data Address Mark at the beginning of a data field. Table 7-12. Description of the READ DELETED DATA Command
Data Bus Phase
Command
R/W
W W W W W W W W W
D7
MT 0
D6
MFM 0
D5
SK 0
D4
0 0
D3
1 0
D2
1 HDS
D1
0 DS1
D0
0 DS0
Remarks
Command Codes Sector ID information before the command execution
____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________ ___________________________ EOT_____________________________ ___________________________ GPL_____________________________ ___________________________ DTL_____________________________
Execution Result R R R R R R R ___________________________ ST0_____________________________ ___________________________ ST1_____________________________ ___________________________ ST2_____________________________ ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________
Data transfer between the FDD and the main system. Status information after command execution Sector ID information after command execution.
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IT8661F
(3) READ A TRACK After receiving a pulse from the INDEX# pin, this READ A TRACK command reads the entire data field from each sector of the track as continuous blocks. If any ID or Data CRC error is found, it continues to read data from the track and indicates the error at the end. Because the MT operation is not allowed with this command, the MT and SK bits should be low during command execution. This command normally terminates when the number of sectors specified by EOT has not been read. After the second occurrence of the INDEX pulse, provided that any ID Address Mark has been found, the FDC will set the IC code in ST0 to 01, indicating an abnormal termination, then finishes this command. Table 7-13. Description of the READ A TRACK Command
Phase
Command
R/W
W W W W W W W W W
Data Bus D7
0 0
D6
MFM 0
D5
SK 0
D4
0 0
D3
0 0
D2
0 HDS
D1
1 DS1
D0
0 DS0
Remarks
Command Codes Sector ID information before the command execution
____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________ ___________________________ EOT_____________________________ ___________________________ GPL_____________________________ ___________________________ DTL_____________________________
Execution Result R R R R R R R ___________________________ ST0_____________________________ ___________________________ ST1_____________________________ ___________________________ ST2_____________________________ ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________
Data transfer between the FDD and main system cylinder contents from index hole to EOT. Status information after command execution Sector ID information after command execution.
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IT8661F
(4) WRITE DATA Each WRITE operation begins with a WRITE DATA command and terminates when data is written into the sector data field, from the host via the FIFO. After, the FDC computes the CRC value and stores it in the CRC field. The sector number in "R" is incremented by one, and the next data operation is performed (Multi Sector WRITE Operation). During this operation, when a terminal count signal or an over/underrun occurs, the remaining data field is filled with 0s. The operation of WRITE DATA command is similar to that of READ DATA command in many aspects, such as transfer capacity, end of the cylinder bit, no data bit, and ID information. The definition of DTL for those cases in N is the same as "no" or 0, etc. Table 7-14. Description of the WRITE DATA Command
Phase
Command
R/W
W W W W W W W W W
Data Bus D7
MT 0
D6
MFM 0
D5
0 0
D4
0 0
D3
0 0
D2
1 HDS
D1
0 DS1
D0
1 DS0
Remarks
Command Codes Sector ID information before the command execution
____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________ ___________________________ EOT_____________________________ ___________________________ GPL_____________________________ ___________________________ DTL_____________________________
Execution Result R R R R R R R ___________________________ ST0_____________________________ ___________________________ ST1_____________________________ ___________________________ ST2_____________________________ ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________
Data transfer between the FDD and main system Status information after command execution Sector ID information after command execution.
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IT8661F
(5) WRITE DELETED DATA This command is the same as the WRITE DATA command, except a Deleted Data Address Mark is written at the beginning of the data field. Table 7-15. Description of the WRITE DELETED DATA Command
Phase
Command
R/W
W W W W W W W W W
Data Bus D7
MT 0
D6
MFM 0
D5
0 0
D4
0 0
D3
1 0
D2
0 HDS
D1
0 DS1
D0
1 DS0
Remarks
Command Codes Sector ID information before the command execution
____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________ ___________________________ EOT_____________________________ ___________________________ GPL_____________________________ ___________________________ DTL_____________________________
Execution Result R R R R R R R ___________________________ ST0_____________________________ ___________________________ ST1_____________________________ ___________________________ ST2_____________________________ ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________
Data transfer between the FDD and main system Status information after command execution Sector ID information after command execution.
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IT8661F
(6) FORMAT A TRACK This command is used to format an entire track. Initialized by an INDEX pulse, it writes data to the gaps, address marks, ID fields, and data fields. The gaps and data field values are controlled by the hostspecified values programmed into N, SC, GPL, and D. The data field is filled with the data byte specified by D. Four data bytes per sector of the ID field: C, H, R, and N are supplied by the host. The C, R, H, and N values must be renewed for every new sector of a track. Only the R value must be changed when a sector is formatted, allowing the disk to be formatted with non-sequential sector addresses. These steps will continue until a new INDEX pulse or the command terminal signal is received. Table 7-16. Description of the FORMAT A TRACK Command
Phase
Command
R/W
W W W W W W
Data Bus D7
0 0
D6
MFM 0
D5
0 0
D4
0 0
D3
1 0
D2
1 HDS
D1
0 DS1
D0
1 DS0
Remarks
Command Codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte FDC formats an entire cylinder
____________________________ N ______________________________ ____________________________SC______________________________ ___________________________ GPL_____________________________ _____________________________D______________________________
Execution Result ___________________________ ST0_____________________________ ___________________________ ST1_____________________________ ___________________________ ST2_____________________________ ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________ In this case, the ID information has no meaning Status information after command execution
R R R R R R R
Control Commands A special feature of these commands is that they don't transfer any data. Only three (3) generate interrupts when finished (READ ID, RE-CALIBRATE, and SEEK).
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IT8661F
(7) READ ID This command, used to find the actual recording head position, stores at the same time as it reads the first ID field value into the FDC registers. If this doesn't occur even when the second INDEX pulse is issued, an abnormal termination will be generated by setting the IC code in the ST0 to 01. Table 7-17. Description of the READ ID Command
Phase
Command Execution
R/W
W W
Data Bus D7
0 0
D6
MFM 0
D5
0 0
D4
0 0
D3
1 0
D2
0 HDS
D1
1 DS1
D0
0 DS0
Remarks
Command Codes The first correct ID information on the cylinder is stored in Data Register
Result
R R R R R R R
___________________________ ST0_____________________________ ___________________________ ST1_____________________________ ___________________________ ST2_____________________________ ____________________________ C ______________________________ ____________________________ H ______________________________ ____________________________ R ______________________________ ____________________________ N ______________________________
Status information after command execution Sector ID information during execution phase
(8) RE-CALIBRATE This command retracts the READ/WRITE head to the track 0 position, resetting the value of the PCN counter and checking the TK00# status. If TK00# is low the DIR# pin remains low; if TK00# is high, SE and EC bits are set high, and the command is finished. When TK00# remains low for 77 step pulses, the command is terminated by setting SE and EC bits as described previously. Because of this, if the disk can accommodate more than 80 tracks, more than one RE-CALIBRATE command will be needed to retract the head to the physical track 0. Table 7-18. Description of the RE-CALIBRATE Command
Phase
Command Execution
R/W
W W
Data Bus D7
0 0
D6
0 0
D5
0 0
D4
0 0
D3
0 0
D2
1 0
D1
1 DS1
D0
1 DS0
Remarks
Command Codes Head retracted to Track 0
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IT8661F
(9) SEEK This command controls the READ/WRITE head movement from one track to another. FDC compares PCN's current head position and NCN values after each step pulse to determine the head movement direction, as the following: PCN < NCN: sets direction signal to 1 and issues step pulses PCN > NCN: sets direction signal to 0 and issues step pulses The impulse rate of step pulse is controlled by Stepping Rate Time in the SPECIFY command. The SEEK command will terminate by setting SE to 1 when the comparison result is PCN = NCN. For the parallel SEEK operation, the FDC returns to Non-Busy State after the command phase (in Busy State), allowing another SEEK or RE-CALIBRATE command to be issued. Since the SEEK command doesn't have a result phase, it is recommended that a SENSE INTERRUPT command be issued after each SEEK command, providing verification of the head position. Table 7-19. Description of the SEEK Command
PHASE
Command
R/W
W W W
Data Bus D7
0 0
D6
0 0
D5
0 0
D4
0 0
D3
1 0
D2
1 HDS
D1
1 DS1
D0
1 DS0
Remarks
Command Codes
___________________________ NCN_____________________________ Head is positioned over proper cylinder on diskette
Execution
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IT8661F
(10) SENSE INTERRUPT STATUS This command resets the interrupt signal, and can identify the cause of interrupt via IC code and SE bit of ST0, as shown in the table below: Table 7-20. Interrupt Identification of the SENSE INTERRUPT STATUS Command Interrupt Identification
SE 0 1 1 IC 11 00 01 INTERRUPT DUE TO Polling Normal termination of SEEK or RE-CALIBRATE command Abnormal termination of SEEK or RE-CALIBRATE command
It may be necessary to generate an interrupt under the following conditions: - Before any DATA TRANSFER or READ ID command - After SEEK, RELATIVE SEEK, or RE-CALIBRATE command (no result phase exists) - When a DATA TRANSFER is required during an execution phase in the non-DMA mode Table 7-21. Description of the SENSE INTERRUPT STATUS Command
Phase
Command Result
R/W
W R R
Data Bus D7
0
D6
0
D5
0
D4
0
D3
1
D2
0
D1
0
D0
0
Remarks
Command Codes Status information at the end of each seek operation
___________________________ST0______________________________ ___________________________PCN_____________________________
(11) Sense Drive Status This non-execution phase command provides the drive status information which is saved in ST3 (Status Register 3). Table 7-22. Description of the SENSE DRIVE STATUS Command
Phase
Command Result
R/W
W W R
Data Bus D7
0 0
D6
0 0
D5
0 0
D4
0 0
D3
0 0
D2
1 HDS
D1
0 DS1
D0
0 DS0
Remarks
Command Codes Status information about FDD
___________________________ ST3_____________________________
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IT8661F
(12) SPECIFY The initial values of the HUT (Head Unload Time), HLT (Head Load Time) and SRT (Step Rate Time) are individually set by this command, as shown in the following table: Table 7-23. Description of the SPECIFY Command
Phase
Command
R/W
W W W
Data Bus D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1 ND
Remarks
Command Codes
___________SRT_____________
____________HUT_____________
_______________________HLT__________________________
(13) INVALID If an undefined command is sent to the FDC, then the FDC will terminate the command without interrupt. Bit 6 and bit 7 in the Main Status Register are both high. When the CPU reads Status Register 0 it will find an 80H. Table 7-24. Description of the INVALID Command
Phase
Command
R/W
W
Data Bus D7 D6 D5 D4 D3 D2 D1 D0
________________________invalid codes__________________________
Remarks
INVALID Command Codes (NOOP - FDC goes into stand by state) STO = 80
Result
R
___________________________ ST0_____________________________
48
IT8661F
7.3 Serial Channel Register Description The IT8661F incorporates two enhanced serial channels which perform serial to parallel conversion on received data, and parallel to serial conversion on transmitted data. Individually, they contain a programmable baud rate generator which is capable of dividing the input clock by a number from 1 to 65535; the data rate of each can also be programmed from 115.2K baud to 50 baud. The character options are programmable for one start bit; 1, 1.5 or two stop bits; even, odd, stick or no parity; and privileged interrupts. Table 7-25. Serial Channel Registers Register
Data
DLAB*
0 0 x
Address
Base + 0h Base + 1h Base + 2h Base + 3h Base + 4h Base + 0h Base + 1h Base + 5h Base + 6h Base + 7h
READ
RBR (Receiver Buffer Register) IER (Interrupt Enable Register) IIR (Interrupt Identification Register) LCR (Line Control Register) MCR (Modem Control Register) DLL (Divisor Latch LSB) DLM (Divisor Latch MSB) LSR (Line Status Register) MSR (Modem Status Register) SCR (Scratch Pad Register)
WRITE
TBR (Transmitter Buffer Register) IER FCR (FIFO Control Register) LCR MCR DLL DLM LSR MSR SCR
Control
x x 1 1 x
Status
x x
* DLAB is bit 7 of the Line Control Register.
7.3.1 Data Register TBR and RBR each hold from five to eight data bits. If the transmitted data is fewer than eight bits, it aligns to the LSB. Either received or transmitted data is buffered by a shift register, and is latched first by a holding register. The bit 0 of any word is first received and transmitted. (1) RBR (Read only) This register receives and holds the entering data. It contains a non-accessible shift register which converts the incoming serial data stream to a parallel 8-bit word. (2) TBR (WRITE only) This register holds and transmits the data via a non-accessible shift register. It converts the outgoing parallel data to a serial stream before transmission.
7.3.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR, MCR (1) IER (READ/WRITE) IER is used to enable (or disable) four active high interrupts which activate the interrupt outputs, with its lower four 4 bits: IER(0), IER(1), IER(2), and IER(3). IER(4)~IER(7): These bits are always "0". IER(3): Set this bit high to enable the Modem Status Interrupt when one of the Modem Status Registers changes its bit state. IER(2): Set this bit high to enable the Receiver Line Status Interrupt which is caused when Overrun, Parity, Framing or Break occurs. IER(1): Set this bit high to enable the Transmitter Holding Register Empty Interrupt. IER(0): Set this bit high to enable the Received Data Available Interrupt (and Timeout Interrupt in the FIFO mode).
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IT8661F
(2) IIR (Read only) This register facilitates the host CPU to determine interrupt priority and its source. The priority of four existing interrupt levels is as follows: 1. Received Line Status (highest priority) 2. Received Data Ready 3. Transmitter Holding Register Empty 4. Modem Status (lowest priority) When a privileged interrupt is pending and the type of interrupt is stored in the IIR which is accessed by the Host, the serial channel holds back all interrupts and indicates the highest priority pending interrupts to the Host. Any new interrupts will not be acknowledged until the Host access finishes. The contents of the IIR are described in the table below:
Table 7-26. Interrupt Identification Register FIFO Mode Interrupt Identification Register
Bit 3 0 0 0 Bit 2 X 1 1 Bit 1 X 1 0 Bit 0 1 0 0 Priority Level First Second Interrupt Type None Receiver Line Status Received Data Available Character Time-out Indication Transmitter Holding Register Empty Modem Status Transmitter Holding Register Empty CTS#, DSR#, RI#, RSLD# Interrupt Source None OE, PE, FE, or BI Received Data Available LSR READ RBR READ or FIFO drops below the trigger level RBR READ IIR READ if THRE is the Interrupt Source or THR WRITE MSR READ Interrupt Reset Control -
Interrupt Set and Reset Functions
1 0
1 0
0 1
0 0
Second Third
0
0
0
0
Fourth
Note: X = Not Defined
IIR(6), IIR(7): Are set when FCR(0) = 1. IIR(4), IIR(5): Always logic 0. IIR(3): In non-FIFO mode, this bit is a logic 0. In the FIFO mode this bit is set along with bit 2 when a time-out Interrupt is pending. IIR(1), IIR(2): Are used to identify the highest priority pending interrupt. IIR(0): Is used to indicate a pending interrupt in either a hard-wired prioritized or polled environment, with a logic 0 state. When this happens, IIR contents may be used as a pointer to the appropriate interrupt service routine.
50
IT8661F
(3) FCR (WRITE only) This register is used to enable, clear the FIFO, and set the RCVR FIFO trigger level. FCR(6), FCR(7): These bits set the trigger levels for the RCVR FIFO interrupt. FCR(4), FCR(5): Reserved. FCR(3): This bit doesn't affect the Serial Channel operation. RXRDY and TXRDY functions are not available on this chip. FCR(2): This self-clearing bit clears all contents of the XMIT FIFO and resets its related counter to 0 by a logic "1". FCR(1): Setting this self-clearing bit to logic 1 clears all contents of the RCVR FIFO and resets its related counter to 0 (except the shift register). FCR(0): XMIT and RCVR FIFO are enabled when this bit is set high. XMIT and RCVR FIFO's will be disabled and cleared when this bit is cleared to low. This bit has to be a logic 1 if the other bits of the FCR are written to or they will not be properly programmed. When this register changes to non-FIFO mode, all contents will be cleared. (5) Scratch Pad Register (READ/WRITE) This 8-bit register does not control the operation of UART in any way. It is intended as a scratch pad register to be used by programmer to temporarily hold general purpose data. Table 7-27. Baud Rates Using (24MHz / 13) Clock Desired Baud Rate
50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200
Divisor Used
2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1
FCR (7)
0 0 1 1
FCR (6)
0 1 0 1
RCVR FIFO Trigger Level
1 byte 4 bytes 8 bytes 14 bytes
(6) LCR (READ/WRITE) LCR controls the format of the data character and gives the information of the serial line. Its contents are: LCR(7): Divisor Latch Access Bit LCR(6): Break Control LCR(5): Stick Parity Bit LCR(4): Even Parity Select (EPS) LCR(3): Parity Enable (PEN) LCR(2): Stop Bit Select (STB) LCR(1): Word Length Select Bit 1 (WLS 1) LCR(0): Word Length Select Bit 0 (WLS 0) LCR(7): Must be set high to access the Divisor Latches of the baud rate generator
(4) Divisor Latches There are two 8-bit Divisor Latches (DLL and DLM) which store the divisor in a 16-bit binary format. They are loaded during initialization to generate a desired Baud Rate. Baud Rate Generator (BRG) Each serial channel contains a programmable BRG which can take any clock input (from DC to 8 MHz) to generate standard ANSI/CCITT bit rates for the channel clocking, with an external clock oscillator. The DLL or DLM is a number of 16-bit format, providing the divisor range from 1 to 216 to obtain the desired baud rate. The output frequency is 16X data rate.
51
IT8661F
during READ or WRITE operations. It must be set low to access the Data Register (RBR and TBR) or the Interrupt Enable Register. LCR(6): Forces the Serial Output (SOUT) to the spacing state (logic 0) by a logic 1, and will remain until a low level resetting LCR(6), enabling the serial port to alert the terminal in a communication system. LCR(5): When this bit and LCR(3) are high at the same time, the parity bit is transmitted and then detected by receiver, in opposite state by LCR(4) to force the parity to a known state and to check the parity bit in a known state. LCR(4): When parity is enabled (LCR(3) = 1), LCR(4) = 0 selects odd parity, and LCR(4) = 1 selects even parity. LCR(3): A parity bit, between the last data word bit and stop bit, will be generated or checked (transmit or receive data) when LCR(3) is high. LCR(2) specifies the number of stop bits in each serial character, summarized as follows: LCR (2) Word Length No. of Stop Bits
0 1 1 1 1 5 bits 6 bits 7 bits 8 bits 1 1.5 2 2 2
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmission. LCR(0) and LCR(1): Specify the number of
bits in each serial character, encoded as the following. LCR (1)
0 0 1 1
LCR (0)
0 1 0 1
Word Length
5 bits 6 bits 7 bits 8 bits
52
IT8661F
(7) MCR (READ/WRITE) Controls the interface with the modem or data set (or device emulating a modem). Table 7-28. Modem Control Register Bits MCR Bits
MCR(7) 0 MCR(6) 0 MCR(5) 0 MCR(4) Loop MCR(3) Interrupt (INT) Enable MCR(2) 0 MCR(1) Request to Send (RTS#) MCR(0) Data Terminal Ready (DTR#) RTS# Output Low DTR# Output Low RTS# Output High DTR# Output High Loop Enabled INT Enabled Loop Disabled INT Disabled
Logic 1
Logic 0
7.3.3 Status Register LSR and MSR MCR(5)~MCR(7): Are always low. MCR(4): Provides a loopback feature for a diagnostic test of the serial channel when it is set high. Serial Output (SOUT) is set to the Marking State Shift Register output loops back into the Receiver Shift Register. All Modem Control inputs (CTS#, DSR#, RI# and RLSD#) are disconnected, the four Modem Control outputs (DTR#, RTS#, OUT1 and OUT2) are internally connected to the four Modem Control inputs and forced to inactive high. The transmitted data is immediately received, allowing the processor to verify the transmit and receive data path of the serial channel. MCR(3): Is the Output 2 bit and enables the serial port interrupt output by a logic 1. MCR(2): Controls the Output 1 bit, which does not have an output pin and can only be read or written by the CPU. MCR(1): Controls the Request to Send (RTS#) which is in an inverse logic state with that of MCR(1). MCR(0): Controls the Data Terminal Ready (DTR#) which is in an inverse logic state with that of the MCR(0). (1) LSR (READ/WRITE) This register provides status indications and is usually the first register read by the CPU to determine the cause of an interrupt or to poll the status of each serial channel. The contents of the LSR are described below: LSR(7): In 16450 mode, this bit is always 0. In the FIFO mode, it is set high when there is at least one parity error, framing or break interrupt in the FIFO. This bit is cleared when the CPU reads LSR, if there are no subsequent errors in the FIFO. LSR(6): This read-only bit indicates that the Transmitter Holding Register and Transmitter Shift Register are both empty, otherwise, this bit is "0". It has the same function in the FIFO mode. LSR(5): Transmitter Holding Register Empty (THRE). This read-only bit indicates that the TBR is empty and ready to accept a new character for transmission. It is set high when a character is transferred from the THR into the Transmitter Shift Register, causing a priority 3 IIR interrupt which is cleared by a read of IIR. In the FIFO mode, it is set when the XMIT FIFO is empty and it is cleared when at least one (1) byte is written to the XMIT FIFO. LSR(4): Break Interrupt (BI) status bit which indicates that the last character received was a break character, (invalid but entire character), including parity and stop bits. This happens when the received data input is held 53
IT8661F
in the spacing (logic 0) for longer than a full word transmission time (start bit + data bits + parity + stop bit). When any of these error conditions is detected (LSR(1) to LSR(4)), a Receiver Line Status interrupt (priority 1) will be produced in the IIR, with the IER(2) previously enabled. LSR(3): Framing Error (FE) bit, a logic 1, indicates that the stop bit in the received character was not valid. It resets low when the CPU reads the contents of LSR. LSR(2): Indicates the parity error (PE) with a logic 1 indicating that the received data character does not have the correct even or odd parity, as selected by LCR(4). It will be reset to "0" whenever the LSR is read by CPU. LSR(1): Overrun Error (OE) bit which indicates by a logic 1 that the RBR has been overwritten by the next character before it had been read by the CPU. In the FIFO mode, the OE occurs when the FIFO is full and the next character has been completely received by the Shift Register. It will be reset when the LSR is read by the CPU. LSR(0): Data Ready (DR) bit logic "1", which indicates a character has been received by RBR, and logic "0" indicating all of the data in RBR or RCV FIFO has been read.
Table 7-29. Line Status Register Bits LSR Bits
LSR(7) PE/FE/BI (FIFO mode) LSR(6) Transmitter Empty(TEMT) LSR(5) Transmitter Holding Register Empty(THRE) LSR(4) Break Interrupt(BI) LSR(3) Framing Error(FE) LSR(2) Parity Error(PE) LSR(1) Overrun Error(OE) LSR(0) Data Ready(DR)
Logic 1
Error Empty Empty Break Error Error Error Ready
Logic 0
No error Not empty Not empty No break No error No error No error Not ready
(2) MSR (READ/WRITE) This 8-bit register provides the current state of the control lines from modems or peripheral devices. In addition to this current state information, four of these eight bits MSR(4) MSR(7) can provide change information when a modem control input changes state. It will be reset to low when the Host reads the MSR. MSR(7): Receive Line Signal Detect Indicates the complement status of Receive Line Signal Detect (RLSD#) input. If MCR(4) = 1, MSR(7) is equivalent to OUT2 of the MCR. MSR(6): Ring Indicator (RI#) - Indicates the complement to the RI# input. If MCR(4)=1, MSR(6) is equivalent to OUT1 in the MCR. MSR(5): Data Set Ready (DSR#) - Indicates that the modem is ready to provide received
data to the serial channel receiver circuitry. If the serial channel is in the loop mode (MCR(5) = 1), MSR(5) is equivalent to DTR# in the MCR. MSR(4): Clear to Send (CTS#) - Indicates the complement of CTS# input. If the serial channel is in the loop mode (MCR(4)=1), MSR(5) is equivalent to RTS# in the MCR. MSR(3): Delta Receiver Line Signal Detect (DRLSD) - Indicates that the RLSD# input state has been changed since the last time the Host read it. MSR(2): Trailing Edge of Ring Indicator (TERI) - Indicates that the RI input state to the serial channel has been changed from a low to high since the last time the Host read it. The change to logic 1 doesn't activate the TERI. 54
IT8661F
MSR(1): Delta Data Set Ready (DDSR) - A logic "1" indicates that the DSR# input to the serial channel has changed state since the last time it was read by the Host. MSR(0): Delta Clear to Send (DCTS) - This bit indicates that the CTS# input state to the serial channel has been changed since the last time it was read by the Host.
Table 7-30. Modem Status Register Bits MSR Bits
MSR(7) MSR(6) MSR(5) MSR(4) MSR(3) MSR(2) MSR(1) MSR(0)
Mnemonic
RLSD# RI# DSR# CTS# DRLSD TERI DDSR DCTS Ring Indicator
Description
Receiver Line Signal Detect Data Set Ready Clear To Send Delta Receiver Line Signal Detect Trailing Edge of Ring Indicator Delta Data Set Ready Delta Clear to Send
7.3.4 Reset Reset of IT8661F should be held to an idle mode reset high for 500ns until initialization causes the following: 1. Initialization of the transmitter receiver internal clock counters. and 2. Resetting all bits of LSR, (except LSR(5) and LSR(6), THRE and TEMT (they are set only by a hardware reset), all bits of MCR and all corresponding discrete lines, memory and logic elements. Before resetting, the IT8661F remains in the idle mode until programmed
Table 7-31. Reset Control of Registers and Pinout Signals Register/Signal Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register SOUT0, SOUT1 RTS0#, RTS1#, DTR0#,DTR1# IRQ of Serial Port Reset Control Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Status All bits Low Bit 0 is high and bits 1-7 are low All bits Low All bits Low All bits Low Bits 5, 6 are high, others are low. Bits 0-3 low, bits 4-7 input signals High High High Impedance
55
IT8661F
7.3.5 Programming Each serial channel of IT8661F is programmed by control registers, whose contents define the character length, number of stop bits, parity, baud rate and modem interface. Even though the control register can be written in any order, the IER should be last because it controls the interrupt enables. After the port is programmed, these registers can still be updated whenever the port is not transferring data. 7.3.6 Software Reset This method allows returning to a completely known state without a SYSTEM RESET. It consists of writing the required data to the LCR, DLL, DLM and MCR. The LSR and RBR must be read before enabling interrupts to clear out any residual data or status bits which may be invalid for subsequent operations. 7.3.7 Clock Input Operation The input frequency of the Serial Channel is 24MHz / 13, not exactly 1.8432MHz. 7.3.8 FIFO Interrupt Mode Operation (1) RCVR Interrupt When set FCR(0)=1 and IER(0)=1, the RCVR FIFO and receiver interrupts are enabled. The RCVR interrupt occurs under the following conditions: a. The receive data available interrupt and the IIR, receive data available indication, will be issued only if the FIFO has reached its programmed trigger level. They will be cleared as soon as the FIFO drops below its trigger level. b. The receiver line status interrupt has higher priority than the received data available interrupt. c. The time-out timer will be reset after receiving a new character or after the Host reads the RCVR FIFO whenever a time-out interrupt occurs. The timer will be reset when the Host reads one character from the RCVR FIFO. RCVR FIFO time-out Interrupt: By enabling RCVR FIFO and receiver interrupts, the RCVR FIFO time-out interrupt will occur under the following conditions: a. It will occur only if there is at least one character in the FIFO whenever the period between the most recent received serial character and the most recent Host read from the FIFO is longer than four consecutive character times. b. The RLCK clock signal input is used to calculate character times. c. The time-out timer will be reset after receiving a new character or after the Host reads the RCVR FIFO whenever any time-out interrupt occurs. The timer will be reset when the Host reads one character from the RCVR FIFO. (2) XMIT Interrupt By setting FCR(0) and IER(1) to high, the XMIT FIFO and transmitter interrupts are enabled, and the XMIT interrupt will occur as follows: a. The transmitter interrupt will occur when the XMIT FIFO is empty, and it will be reset if the THR is written or the IIR is read. b. The transmitter FIFO empty indications will be delayed one character time minus the last stop bit time whenever the following condition occurs: THRE = 1 and there has not been at least two bytes in the transmitter FIFO at the same time since the last THRE = 1. The transmitter interrupt after changing FCR(0) will be immediate. Once it is enabled, the THRE indication is delayed one (1) character time minus the last stop bit times. The character time-out and RCVR FIFO trigger level interrupts are in the same priority order as the received data available interrupt. The XMIT FIFO empty is in the same priority as the transmitter holding register empty interrupt. FIFO Polled Mode Operation [FCR(0)=1, and IER(0), IER(1), IER(2), IER(3) or all are zero] Either one or both XMIT and RCVR can be in this operation mode which the user program will check RCVR and XMIT status via the LSR as described next page:
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IT8661F
LSR(7): RCVR FIFO error indication LSR(6): XMIT FIFO and Shift register empty LSR(5): The XMIT FIFO empty indication LSR(1) - LSR(4): Specifies that errors have occurred. Character error status is handled the same way as in the interrupt mode. The IIR is not affected since IER(2)=0. LSR(0): Will be high whenever the RCVR FIFO contains at least one byte There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode.
57
IT8661F
7.4 Parallel Port The IT8661F incorporates one multi-mode high performance parallel port. The IT8661F supports the IBM AT, PS/2 compatible bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP). Refer to IT8661F Configuration registers and Hardware Configuration Description for information on the following: enabling/ disabling, changing the base address of the parallel port, and selecting the mode of operation.
Table 7-32. Parallel Port Connector in Different Modes Host Connector
1 2-9 10 11 12 13 14 15 16 17
Pin No.
76 71-68,66-63 62 61 60 59 77 75 73 74
SPP
STB# PD0 - 7 ACK# BUSY PE SLCT AFD# ERR# INIT# SLIN#
EPP
WRITE# PD0 - 7 INTR WAIT# (NU) (1) (NU) (1) DSTB# (NU) (1) (NU) (1) ASTB# nStrobe PD0 - 7 nAck
ECP
Busy PeriphAck(2) PError nAckReverse(2) Select nAutoFd HostAck(2) nFault nPeriphRequest(2) nInit nReverseRequest(2) nSelectIn
Notes: 1. NU: Not used 2. Fast mode 3. For more information, please refer to the IEEE 1284 standard
7.4.1 SPP and EPP Modes Table 7-33. Address Map and Bit Map for SPP and EPP Modes Register
Data Port Status Port Control Port EPP Address Port EPP Data Port0 EPP Data Port1 EPP Data Port2 EPP Data Port3
Address
Base 1+0H Base 1+1H Base 1+2H Base 1+3H Base 1+4H Base 1+5H Base 1+6H Base 1+7H
I/O
R/W R R/W R/W R/W R/W R/W R/W
D0
PD0 TMOUT STB PD0 PD0 PD0 PD0 PD0
D1
PD1 1 AFD PD1 PD1 PD1 PD1 PD1
D2
PD2 1 INIT PD2 PD2 PD2 PD2 PD2
D3
PD3
D4
PD4
D5
PD5 PE
D6
PD6
D7
PD7
Mode
SPP/EPP
ERR# SLCT SLIN PD3 PD3 PD3 PD3 PD3
ACK# BUSY# SPP/EPP 1 PD6 PD6 PD6 PD6 PD6 1 PD7 PD7 PD7 PD7 PD7 SPP/EPP EPP EPP EPP EPP EPP
IRQE PDDIR PD4 PD4 PD4 PD4 PD4 PD5 PD5 PD5 PD5 PD5
Note 1. The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60, 0X61).
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IT8661F
(1) Data Port (Base Address 1 + 00h) This is a bi-directional 8-bit data port. The direction of data flow is determined by bit 5 of the logic state of the control port register. It forwards directions when the bit is low and reverses when the bit is high. (2) Status Port (Base Address 1 + 01h) This is a read only register. Writing to this register has no effect. The contents of this register are latched during an IOR cycle. Bit 7 - BUSY#: Inverse of printer BUSY signal, a logic "0" means that the printer is busy and cannot accept another character. A logic "1" means that it is ready to accept the next character. Bit 6 - ACK#: Printer acknowledge, a logic "0" mean that the printer has received a character and ready to accept another. A logic "1" means that it is still processing the last character. Bit 5 - PE: Paper end, A logic "1" indicates paper end. Bit 4 - SLCT: Printer selected, a logic "1" means that the printer is on line. Bit 3 - ERR#: Printer error signal, a logic "0" means an error has been detected. Bits 1, 2: Reserved, these bits are always "1" when read. Bit 0 - TMOUT: This bit is valid only in EPP mode and indicates that a 10-msec time out has occurred in EPP operation. A logic "0" means no time out and a logic one means that a time out error has been detected. This bit is cleared by a RESET or writing a logic "1" to it. When IT8661F is selected to non-EPP mode (SPP or ECP), this bit is always logic "one" when read. (3) Control Port (Base Address 1 + 02h) This port provides all output signals to control the printer. The register can be read and written. Bits 6, 7: Reserved, these two bits are always "one" when read. Bit 5 PDDIR: Data port direction control, this bit determines the direction of the data port. Set this bit "0" to output the data port to PD bus and "1" to input from PD bus. Bit 4 IRQE: Interrupt request enable, setting this bit "1" enables interrupt requests from the parallel port to the Host. An interrupt request is generated by a "zero" to "one" transition of the ACK# signal. Bit 3 SLIN: Inverse of SLIN# pin, setting this bit to "1" selects the printer. Bit 2 INIT: Initiate printer, setting this bit to "0" initializes the printer. Bit 1 AFD: Inverse of the AFD# pin, setting this bit to "1" causes the printer to automatically feed after each line is printed. Bit 0 STB: Inverse of the STB# pin. This pin controls the data strobe signal to printer. (4) EPP Address Port (Base Address 1 + 03h) The EPP Address Port is only available in EPP mode. When the Host writes to this port, the contents of D0 -D7 are buffered and output to PD0 - PD7. The leading edge of IOW causes an EPP ADDRESS WRITE cycle. When the Host reads from this port, the contents of PD0 - PD7 are read. The leading edge of IOR causes an EPP ADDRESS READ cycle. (5) EPP Data Port 0-3 (Base Address 1 + 04-07h) The EPP Data Ports are only available in EPP mode. When the Host writes to these ports, the contents of D0 - D7 are buffered and output to PD0 - PD7. The leading edge of IOW causes an EPP DATA WRITE cycle. When the Host reads from these ports, the contents of PD0 - PD7 are read. The leading edge of IOR causes an EPP DATA READ cycle. 7.4.2 EPP Mode Operation When the parallel port of IT8661F is selected to be in EPP mode, the SPP mode is also available, if no EPP Address/Data Port address is decoded (Base address + 03h07h), the PD bus is in the SPP mode, and the output signals such as STB#, AFD#, INIT#, and SLIN# are set by the SPP control port. The direction of the data port is controlled by bit 5 of the control port register. There is a 10msec time required to prevent the system from lockup. The time has elapsed from the beginning of the IOCHRDY high (EPP READ/WRITE cycle) to WAIT# being 59
IT8661F
de-asserted. If a time-out occurs, the current EPP READ/WRITE cycle is aborted and a logic "1" will be read in the status port register Bit 0. The Host must write 0 to bits 0, 1, 3 of the control port register, before any EPP READ/WRITE cycle (EPP spec.) The pins STB#, AFD# and SLIN# are controlled by hardware for the hardware handshaking during EPP READ/WRITE cycle. (1) EPP ADDRESS WRITE 1. The Host writes a byte to the EPP Address Port (Base address + 03h). The chip drives D0 - D7 onto PD0 - PD7. 2. The chip drives IOCHRDY low and asserts WRITE# (STB#) and ASTB# (SLIN#) after IOW becomes active. 3. Peripheral de-asserts WAIT, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts ASTB#, latches the address from D0 - D7 to PD bus and releases IOCHRDY, allowing the Host to complete the I/O WRITE cycle. 4. Peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. Then, the chip de-asserts WRITE to terminate the cycle. (2) EPP ADDRESS READ 1. The Host reads a byte from the EPP Address Port. The chip drives PD bus to tristate for peripheral to drive. 2. The chip drives IOCHRDY low and asserts ASTB# after IOR becomes active. 3. Peripheral drives PD bus valid and deasserts WAIT, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts ASTB#, latches the address from PD bus to D0 -D7 and releases IOCHRDY, allowing the Host to complete the I/O READ cycle. 4. Peripheral drives PD bus to tristate and then asserts WAIT#, indicating that it acknowledges the termination of the cycle. (3) EPP DATA WRITE 1. The host writes a byte to the EPP Data Port (Base address +04H - 07H). The chip drives D0- D7 onto PD0 -PD7. 2. The chip drives IOCHRDY low and asserts WRITE# (STB#) and DSTB (AFD#) after IOW becomes active. 3. Peripheral de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts DSTB#, latches the data from D0 - D7 to PD bus and releases IOCHRDY, allowing the Host to complete the I/O WRITE cycle. 4. Peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. Then, the chip de-asserts WRITE to terminate the cycle. (4) EPP DATA READ 1. The Host reads a byte from the EPP DATA Port. The chip drives PD bus to tristate for peripheral to drive. 2. The chip drives IOCHRDY low and asserts DSTB# after IOR becomes active. 3. Peripheral drives PD bus valid and deasserts WAIT#, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts DSTB#, latches the data from PD bus to D0 - D7 and releases IOCHRDY allowing the host to complete the I/O READ cycle. 4. Peripheral tristates PD bus and then asserts WAIT#, indicating that it acknowledges the termination of the cycle. 7.4.3 ECP Mode Operation This mode is both software and hardware compatible with that of the existing parallel ports, allowing ECP to be used as a standard LPT port when ECP is not required. It provides an automatic high-burst-bandwidth channel that supports DMA or ECP in both forward and reverse directions. A 16-byte FIFO is implemented in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The port supports automatic handshaking for the standard parallel port to improve compatibility and expedite the mode transfer. It also supports run-length encoded (RLE) decompression in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how
60
IT8661F
many times a byte is repeated. The IT8661F does not support hardware compression. For a detailed description, please refer to "Extended Capabilities Port Protocol and ISA Interface Standard".
Table 7-34. Bit Map of the ECP Registers Register
data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr 0 0 0 intrValue mode 0 0 1 0 nErrIntrEn
D7
PD7 Addr/RLE nBusy 1
D6
PD6
D5
PD5
D4
PD4
D3
PD3 Address or RLE field
D2
PD2
D1
PD1
D0
PD0
nAck 1
PError PDDIR
Select IRQE
nFault SelectIn
1 nInit
1 AutoFd
1 Strobe
Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 0 dmaEn 0 0 ServiceIntr 0 0 full 0 0 empty
(1) ECP Register Definitions Table 7-35. ECP Register Definitions Name
data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
Address
Base 1 +000H Base 1 +000H Base 1 +001H Base 1 +002H Base 2 +000H Base 2 +000H Base 2 +000H Base 2 +000H Base 2 +001H Base 2 +002H
I/O
R/W R/W R/W R/W R/W R/W R/W R R/W R/W
ECP Mode
000-001 011 All All 010 011 110 111 111 All
Function
Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Note 1: The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60, 0X61). 2: The Base address 2 depends on the Logical Device configuration registers of Parallel Port (0X62, 0X63).
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(2) ECP Mode Descriptions Table 7-36. ECP Mode Descriptions Mode
000 001 010 011 110 111 Standard Parallel Port Mode PS/2 Parallel Port Mode Parallel Port FIFO Mode ECP Parallel Port Mode Test Mode Configuration Mode
Description
Note: Please refer to the ECP Register Description on pages 62-64 for a detailed description of mode selection.
(3) ECP Pin Descriptions Table 7-37. ECP Pin Descriptions Pin
76 71-68, 66-63 62 61
Name
nStrobe (HostClk) PD0~PD7 nACK (PeriphClk) Busy (PeriphACK)
Type
O I/O I I
Description
Used for handshaking with Busy to write data and addresses into the peripheral device Address or data or RLE data Used for handshaking with nAutoFd to transfer data from the peripheral device to the Host. The peripheral uses this signal for flow control in the forward direction (handshaking with nStrobe). In the reverse direction, this signal is used to determine whether command or data information is present on PD0~PD7. Used to acknowledge nInit from the peripheral that drives this signal low, permitting the host to drive the PD bus. Printer On-Line indication In the reverse direction, it is used for handshaking between the nACK and the Host. When it is asserted, a peripheral data byte is requested. In the forward direction, this signal is used to determine whether command or data information is present on PD0 ~ PD7. In the forward direction (only), the peripheral is permitted (but not required) to assert this signal (low) to request a reverse transfer while in ECP mode. The signal provides a mechanism for peer-to-peer communication. It is typically used to generate an interrupt to host, which has ultimate control over the transfer direction. The host may drive this signal low to place PD bus in the reverse direction. In ECP mode, the peripheral is permitted to drive the PD bus when nInit is low and nSelect is high Always inactive (high) in ECP mode
60 59 77
PError (nAckReverse) Select nAutoFd (HostAck)
I I O
75
nFault (nPeriphRequest)
I
73
nInit (nReverseRequest) nSelectIn (1284 Active)
O
74
O
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IT8661F
(4) Data Port (Base 1+00h, Modes 000 and 001) Its contents will be cleared by a RESET. In a WRITE operation, the contents of the data bus are latched by the Data Register at the rising edge of the IOW# input. The contents are then sent without being inverted to PD0~ PD7. In a READ operation, the contents of data ports are read and sent to the host. (5) ecpAFifo Port (Address/RLE) (Base 1 +00h, Mode 011) Any data byte written to this port is placed in the FIFO and tagged as an ECP Address/RLE. Then the hardware automatically sends this data to the peripheral. Operation of this port is valid only in the forward direction (dcr(5)=0). (6) Device Status Register (dsr) (Base 1 +01h, Mode All) Bits 0, 1 and 2 of this register are not implemented. They remain at high in a READ operation of the Printer Status Register. dsr(7): This bit is the inverted level of the Busy input. dsr(6): This bit is the state of the nAck input. dsr(5): This bit is the state of the PError input. dsr(4): This bit is the state of the Select input. dsr(3): This bit is the state of the nFault input. dsr(2)~dsr(0): These bits are always 1. (7) Device Control Register (dcr) (Base 1+02h, Mode All) Bits 6 and 7 of this register have no function. They are set high during the READ operation, and cannot be written. Contents in bits 0~5 are initialized to zero when the RESET pin is active. dcr(7)~dcr(6): These two bits are always high. dcr(5): Except in modes 000 and 010, setting this bit low means that the PD bus is in output operation; setting it high, in input operation. This bit will be forced to low in mode 000. dcr(4): Setting this bit high enables interrupt request from peripheral to host due to a rising edge of the nAck input. dcr(3): It is inverted and output to SelectIn. dcr(2): It is output to nInit without inversion. dcr(1): It is inverted and output to nAutoFd. dcr(0): It is inverted and output to nStrobe. (8) Parallel Port Data FIFO (cFifo) (Base 2+00h, Mode 010) Bytes written or DMA transferred from the Host to this FIFO are sent by a hardware handshake to the peripheral according to standard parallel port protocol. This operation is only defined for the forward direction. (9) ECP Data FIFO (ecpDFifo) (Base 2+00h, Mode 011) When the direction bit dcr(5) is 0, bytes written or DMA transferred from the Host to this FIFO are sent by hardware handshaking to the peripheral according to the ECP parallel port protocol. When dcr(5) is 1, data bytes from the peripheral to this FIFO are read in an automatic hardware handshaking. The Host can get these bytes by making READ operations or DMA transfers from this FIFO. (10) Test FIFO Mode (tFifo) (Base 2+00h, Mode 100) The Host may operate READ/WRITE or DMA transfers to this FIFO in any direction. Data in this FIFO will be displayed on the PD bus without using hardware protocol handshaking. The tFifo will not accept new data after it is full. Making a READ from an empty tFifo causes the last data byte to be returned. (11) Configuration Register A (cnfgA) (Base 2+00h, Mode 111) This read-only register indicates to the system that interrupts are ISA-Pulses. This is an 8 bit implementation by returning a 10h. (12) Configuration Register B (cnfgB) (Base 2+01h, Mode 111) This register is read-only. cnfgB(7): Logic zero read indicates that the chip does not support hardware RLE compression.
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cnfgB(6): Returns the value on the ISA IRQ line to warn of possible conflicts. cnfgB(5)~cnfg(3): A value 000 read indicates that the interrupt must be selected with jumpers. cnfgB(2)~cnfg(0): A value 000 read indicates that the DMA channel is jumpered 8-bit DMA. (13) Extended Control Register (ecr) (Base 2+02h, Mode All) ECP function control register. ecr(7)~ecr(5): These bits are used for READ/WRITE and Mode selection.
Table 7-38. Extended Control Register (ECR) Mode and Description ECR
000
Mode and Description
Standard Parallel Port Mode. The FIFO is reset and the direction bit dcr(5) is always 0 (forward direction) in this mode.
001
PS/2 Parallel Port Mode. It is similar to the SPP mode, except that the dcr(5) is READ/WRITE. When dcr(5) is 1, the PD bus is tristate. Reading the data port returns the value on the PD bus instead of the value of the data register.
010
Parallel Port data FIFO Mode. This mode is similar to the 000 mode, except that the Host writes or DMA transfers the data bytes to the FIFO. Then the FIFO data is sent to the peripheral using the standard parallel port protocol automatically. This mode is only valid in the forward direction (dcr(5)=0).
011
ECP Parallel Port Mode. In the forward direction, bytes placed into the ecpDFifo and ecpAFifo are placed in a single FIFO and automatically sent to the peripheral under ECP protocol. In the reverse direction, bytes are sent to the ecpDFifo from ECP port.
100, 101 110 111
Reserved, not defined Test mode. In this mode, the FIFO may be read from or written to, but it cannot be sent to peripheral. Configuration mode. In this mode, the cnfgA and cnfgB registers are accessible at 0x400 and 0x401
ecr(4): nErrIntrEn, READ/WRITE, Valid in ECP(011) Mode 1: Disables the interrupt generated on the asserting edge of the nFault input. 0: Enables the interrupt pulse on the asserting edge of the nFault. An interrupt pulse will be generated if nFault is asserted, or if this bit is written from 1 to 0 in the low level nFault. ecr(3): dmaEn, READ/WRITE 1: Enables DMA. DMA starts when serviceIntr (ecr(2)) is 0. 0: Disables DMA unconditionally. ecr(2) : serviceIntr, READ/WRITE 1: Disables DMA and all service interrupts 0: Enables the service interrupts. This bit will be set to one (1) by hardware when
one of the three service interrupts has occurred. Writing 1 to this bit will not generate an interrupt. Case 1: dmaEn=1 During DMA, this bit is set to 1 (a service interrupt generated) when terminal count is reached. Case 2: dmaEn=0, dcr(5)=0 This bit is set to 1 (a service interrupt generated) whenever there are writeIntrThreshold or more bytes space free in the FIFO. Case 3: dmaEn=0, dcr(5)=1 This bit is set to 1 (a service interrupt generated) whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. 64
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ecr(1): full, read-only 1: The FIFO is full and cannot accept another byte. 0: The FIFO has at least 1 free data byte space. ecr(0): empty, read only 1: The FIFO is empty. 0: The FIFO contains at least 1 data byte. (14) Mode Switching Operation In programmed I/O control (mode 000 or 001), P1284 negotiation and all other tasks that happen before data is transferred, are software controlled. Setting mode to 011 or 010 will cause the hardware to perform an automatic control-line handshaking, transferring information between FIFO and the ECP port. From mode 000 or 001, any other mode may be immediately switched to from another mode. To change direction, the mode must first be set to 001. In extended forward mode, FIFO must be clear and all the signals must be de-asserted before returning to mode 000 or 001. In ECP reverse mode, all data must be read from the FIFO before returning to mode 000 or 001. Usually, unneeded data is accumulated during ECP reverse handshaking, when mode changes during a data transfer. In such conditions, nAutoFd will be de-asserted regardless of the transfer state. To avoid bugs during handshaking signals, these guidelines must be followed. (15) Software Operation (ECP) Before ECP operation can begin, it is first necessary for the Host to switch the mode to 000 in order to negotiate with the parallel port. During this process, the Host determines whether peripheral supports ECP protocol. After this negotiation, mode is set to 011 (ECP). To enable the drivers, direction must be set to 0. Both strobe and autoFd are set to 0, causing nStrobe and nAutoFd signals to be de-asserted. All FIFO data transfers are PWord wide and PWord aligned. Permitted only in the forward direction, address/RLE transfers are bytewide. ECP address/RLE bytes may be automatically sent by writing the ecpAFifo. Similarly, data PWords may be automatically sent via ecpDFifo. 65 To change directions, the Host switches mode to 001. It then negotiates either the forward or reverse channel, sets direction to 1 or 0, and finally switches mode to 001. If the direction is set to 1, the hardware performs handshaking for each ECP data byte read, then tries to fill the FIFO. At this time, PWords may be read from the expDFifo while it retains data. It is also possible to perform ECP transfers by handshaking with individual bytes under program control in mode = 001, or 000, even though this is a comparatively timeconsuming approach. (16) Hardware Operation (DMA) Standard PC DMA protocol is followed. As in the programmed I/O case, software sets THE direction and state. Next, the desired count and memory address are programmed into DMA controller. The dmaEn is set to 1, and the serviceIntr is set to 0. To complete the process, the DMA channel with the DMA controller is unmasked. The contents in the FIFO are emptied or filled by DMA using the right mode and direction. DMA is always transferred to or from the FIFO located at 0 x 400. By generating an interrupt and asserting a serviceIntr, DMA is disabled when the DMA controller reaches the terminal count. By not asserting dREQ for more than 32 consecutive DMA cycles, blocking of refresh requests is eliminated. When it is necessary to disable a DMA while performing a transfer, the host DMA controller is disabled, serviceIntr is then set either to 1, and dmaEn is next set to 0. If Either the contents in FIFO are empty or full, the DMA will start again. This is first done by enabling the host DMA controller, then setting dmaEn to 1. Finally, serviceIntr is set to 0. Upon completion of a DMA transfer in the forward direction, the software program must wait until the contents in FIFO are empty and the busy line is low, ensuring that all data successfully reaches the peripheral device. (17) Interrupts It is necessary to generate an interrupt when any of the following states are reached. 1. serviceIntr = 0, dmaEn = 0, direction = 0, and the number of PWords in FIFO is greater than or equal to writeIntrThreshold.
IT8661F
2. serviceIntr = 0, dmaEn = 0, direction = 1, and the number of full PWords in the FIFO is greater than or equal to readIntrThreshold. 3. serviceIntr = 0, dmaEn = 1, and DMA reaches the terminal count. 4. nErrIntrEn = 0 and nFault goes from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. 5. ackIntEn = 1. In current implementations using existing parallel ports, the interrupt generated may be either edge or level type, making it "ISA-friendly". (18) Interrupt Driven Programmed I/O It is also possible to use an interrupt-driven programmed I/O to execute either ECP or parallel port FIFOs. An interrupt will occur in the forward direction when serviceIntr is 0 and the number of free PWords in the FIFO is equal to or greater than writeIntrThreshold. If either of these conditions is not met, it may be filled with writeIntrThreshold PWords. An interrupt will occur in the reverse direction when serviceIntr is 0 and the number of available PWords in the FIFO is equal to readIntrThreshold. If it is full, the FIFO can be completely emptied in a single burst. If it is not full, only a number of PWords equal to readIntrThreshold may be read from the FIFO in a single burst. In the test mode, software can determine the values of writeIntrThreshold, readIntrThreshold, and FIFO depth while accessing the FIFO. Any PC ISA implementation that is adjusted to expedite DMA or I/O transfer must ensure that the bandwidth on the ISA is maintained in the interface. Although the ISA bus of PC cannot be directly controlled, the interface bandwidth of ECP port can be constrained to perform at optimum speed. (19) Standard Parallel Port In the forward direction with DMA, the standard parallel port is run at or near the permitted peak bandwidth of 500KB/sec. The state machine does not examine nAck, but just begins the next DMA based on the Busy signal.
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8. DC Electrical Characteristics
Absolute Maximum Ratings*
Applied Voltage (VCC) ....................... -0.5V to VCC+0.3V Input Voltage (VI)......................................-0.5V to 7.0V Output Voltage (VO). ........................ -0.5V to VCC+0.3V Storage Temperature (TSTG).................. -65 C to 150 C Power Dissipation............................................ 300mW
o o
*Comments
Stresses above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VCC = 5V 5%, Ta = 0C to + 70C) Symbol Parameter Min. Typ. Max. Unit
A
Conditions
General Output Buffer Tri-state Leakage IOZ 3-state Leakage -20 20
I/O12 Type Buffer VOL VOH VIL VIH IIL IIH Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Low Leakage Input High Leakage 2.0 10 -10 2.4 0.8 0.4 V V V V A A VIN = 0 VIN = VCC IOL = 12 mA IOH = -6 mA
I/O24 Type Buffer VOL VOH VIL VIH IIL IIH Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Low Leakage Input High Leakage 2.0 10 -10 2.4 0.8 0.4 V V V V A A VIN = 0 VIN = VCC IOL = 24 mA IOH = -12 mA
O48 Type Buffer VOL VOH Output Low Voltage Output High Voltage 2.4 0.5 V V IOL = 48mA IOH = -12 mA
O24 Type Buffer VOL VOH Output Low Voltage Output High Voltage 2.4 0.4 V V IOL = 24 mA IOH = -12 mA
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DC Electrical Characteristics (cont'd) Symbol Parameter Min. Typ. Max. Unit Conditions
O12 Type Buffer VOL VOH Low Output Voltage High Output Voltage 2.4 0.4 V V IOL = 12mA IOH = -12 mA
OD24 Type Buffer VOL Low Output Voltage 0.4 V IOL = 24 mA
OP12 Type Buffer VOH High Output Voltage 2.4 V IOH = -12 mA
IS Type Buffer VIL VIH IIL IIH Low Input Voltage High Input Voltage Low Input Leakage High Input Leakage 2.0 10 -10 0.8 V V A A VIN = 0 VIN = VCC
OCLK Type Buffer VOL VOH Low Output Voltage High Output Voltage 2.4 0.4 V V IOL = 12mA IOH = -12 mA
ICLK Type Buffer VIL VIH IIL IIH Low Input Voltage High Input Voltage Low Input Leakage High Input Leakage 2.0 10 -10 0.8 V V A A VIN = 0 VIN = VCC
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9. AC Characteristics ( VCC = 5.0V 5%, Ta = 0C to + 70C)
9.1 READ Cycle Timing
A[15-0] AEN t1 t3 t2
IOR # t5
t4 D[7:0]
Valid Data
Table 9-1. READ Cycle Timing Symbol
t1 t2 t3 t4 t5
Parameter
Address setup to IOR# Address hold from IOR# IOR# pulse width IOR# to Data valid Output floating delay from IOR#
Min.
10 10 100 25 25
Typ.
Max.
Unit
ns ns ns
65 50
ns ns
9.2 WRITE Cycle Timing
A0 ~ A15 AEN
t1
IOW #
t3
t2
t4
D0 ~ D7
t5
DATA VALID
Table 9-2. WRITE Cycle Timing Symbol
t1 t2 t3 t4 t5
Parameter
Address setup to IOW# Address hold from IOW# IOW# pulse width Data setup to IOW# Data hold from IOW#
Min.
10 10 100 25 15
Typ.
Max.
Unit
ns ns ns ns ns
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9.3 FDC Timing 9.3.1 DMA Operation Timing
DRQx t1 DACKx#
IOR# IOW# t2,t3
Table 9-3. DMA Operation Timing of FDC Timing Symbol
t1 t2 t3
Parameter
DACKx to DRQx DRQx to IOR# DRQx to IOW#
Min.
Typ.
Max.
100
Unit
ns ns ns
0 0
* The DMA Channel is selected by the configuration register (0X74).
9.3.2 Terminal Count, Index
t1
TC
t2
INDEX#
Table 9-4. Terminal Count, Index of FDC Timing Symbol
t1 t2
Parameter
Terminal count width INDEX# pulse width
Min.
80 100
Typ.
Max.
Unit
ns ns
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9.3.3 FDD WRITE/READ Operation Timing
t1
WDATA#
t2
RDATA#
Table 9-5. FDD WRITE/READ Operation Timing of FDC Timing Symbol
t1 t2
Parameter
WRITE data width (low) READ data width (low)
Min.
Typ.
396/248/ 252 248/396/ 748
Max.
Unit
ns ns
Note: In the typical column of above table, each item includes values for 500/300/250 bps transfer rates respectively.
9.3.4 SEEK Operation Timing
DIR #
t3
t2
STEP
t1
Table 9-6. SEEK Operation Timing of FDC Timing Symbol
t1 t2 t3
Parameter
STEP# active time STEP# cycle time DIR# setup to STEP#
Min.
6 6.104 1
Typ.
Max.
Unit
us ms
2
us
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9.4 Serial Port Timing 9.4.1 Transmitter
UIF0 (TX1,2) t2
START
DATA(5-8)
PARITY
STOP ( 1-2 )
START
DATA( 5-8) t4
IRQx t1 IOW # (WR THR) t3 IOR # (RD IIR) t5
Table 9-7. Transmitter of Serial Port Timing Symbol
t1 t2
Parameter
Delay from falling edge of IOW# (WR THR) to reset interrupt Delay from initial interrupt reset to transmit start (SOUT) Delay from initial write to IRQx active
Min.
Typ.
Max.
80
Unit
ns Baud cycle baud cycle baud cycle ns
8
24
t3
8
24
t4
Delay from stop (SOUT) to IRQx (THRE) Delay from IOR# (RD IIR) to reset IRQx (THRE)
8
24
t5
100
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9.4.2 Modem
IOW # (WR MCR) t2 RTS#, DTR# t1
CTS#, DSR#, RLSD#
t3 t3
IRQx
t4 ( RD MSR )
t5 RT#
Table 9-8. Modem of Serial Port Timing Symbol
t1 t2 t3 t4 t5
Parameter
Delay from IOW# (WR MCR) to output (RTS# or DTR#) high Delay from IOW# (WR MCR) to output (RTS# or DTR#) low Delay to set interrupt IRQx from MODEM input (CTS#, RLSD#, DSR#) Delay to reset interrupt IRQx from IOR# (RD MSR) Delay to set interrupt IRQx from MODEM input (RI#)
Min.
Typ.
Max.
40 40 40 80 40
Unit
ns ns ns ns ns
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9.4.3 Receiver
UIF1,2 (RX1,2) START DATA BITS ( 5-8 ) PARITY STOP
t1
IRQx t2 IOR# ACTIVE
Table 9-9. Receiver of Serial Port Timing Symbol
t1 t2
Parameter
Delay from stop (SIN) to set IRQx Delay from IOR# (RD RBR/RD LSR) to reset interrupt IRQx
Min.
Typ.
8 55
Max.
Unit
clkACE ns
Note: clkACE stands for ACE actual input clock, i.e. 24/13=1.846 MHz internal clock.
9.4.4 IrDA Receive Timing
DATA 1 0 t2 0 t1 1 0 t1 0 1 1 0 1 1
t2
IRRXL
PULSE WIDTH t1 = 3/16 OF BIT TIME t2
Symbol
t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2
Table 9-10. IrDA Receive Timing of Serial Port Timing Parameter Min. Typ. Max.
Pulse Width at 115 kbaud Pulse Width at 57.6 kbaud Pulse Width at 38.4 kbaud Pulse Width at 19.2 kbaud Pulse Width at 9.6 kbaud Pulse Width at 4.8 kbaud Pulse Width at 2.4 kbaud Bit Time at 115 kbaud Bit Time at 57.6 kbaud Bit Time at 38.4 kbaud Bit Time at 19.2 kbaud Bit Time at 9.6 kbaud Bit Time at 4.8 kbaud Bit Time at 2.4 kbaud 1.41 2.82 4.23 7.05 14.1 28.2 56.4 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 2.71 3.69 5.53 11.07 22.13 44.27 88.5
Unit
us us us us us us us us us us ms ms ms ms
Note: IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX.
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9.4.5 IrDA Transmit Timing
DATA
1 0 t2 0 t1
1 0 t1 0
1
1 0
1
1
t2
IRTX
PULSE WIDTH t1 = 3/16 OF BIT TIME t2
Table 9-11. IrDA Transmit Timing of Serial Port Timing Symbol
t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2
Parameter
Pulse Width at 115 kbaud Pulse Width at 57.6 kbaud Pulse Width at 38.4 kbaud Pulse Width at 19.2 kbaud Pulse Width at 9.6 kbaud Pulse Width at 4.8 kbaud Pulse Width at 2.4 kbaud Bit Time at 115 kbaud Bit Time at 57.6 kbaud Bit Time at 38.4 kbaud Bit Time at 19.2 kbaud Bit Time at 9.6 kbaud Bit Time at 4.8 kbaud Bit Time at 2.4 kbaud
Min.
1.41 2.82 4.23 7.05 14.1 28.2 56.4
Typ.
1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416
Max.
2.71 3.69 5.53 11.07 22.13 44.27 88.5
Unit
ms ms ms ms ms ms ms ms ms ms ms ms ms ms
Note: Criteria for Receive Pulse Detection - A received pulse is considered detected if the pulse width is 1.4 ms minimum.
9.4.6 ASKIR Receive Timing
DATA 1 0 0 1 0 0 1 1 0 1 1
t1
t2
IRRXL
t3 MIRSIN
t4
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Table 9-12. ASKIR Receive Timing of Serial Port Timing Symbol
t1 t2 t3 t4
Parameter
Modulated Input Bit Time Off Bit Time Modulated Input "high" Modulated Input "low"
Min.
Typ.
Max.
Unit
us us
0.8 0.8
1 1
1.2 1.2
us us
Note: MIRSIN is the modulated input.
9.4.7 ASKIR Transmit Timing
DATA
1 0 0
1 0 0
1
1 0
1
1
t1
t2
IRTX
t3
t4
MIRSOUT
Table 9-13. ASKIR Transmit Timing of Serial Port Timing Symbol
t1 t2 t3 t4
Parameter
Modulated Output Bit Time Off Bit Time Modulated Output "high" Modulated Output "low"
Min.
Typ.
Max.
Unit
ms ms
0.8 0.8
1 1
1.2 1.2
ms ms
Note: MIRSOUT is the modulated output.
9.5 Parallel Port Timing 9.5.1 Control Signal Delay Time
IOW# ( WR CTRL ) t1,t2,t3,t4 STB#,AFD# INIT#,SLIN#
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Table 9-14. Control Signal Delay Time of Parallel Port Timing Symbol
t1 t2 t3 t4
Parameter
Delay from IOW# (WR CTRL PORT) to STB# valid Delay from IOW# (WR CTRL PORT) to AFD# valid Delay from IOW# (WR CTRL PORT) to INIT# valid Delay from IOW# (WR CTRL PORT) to SLIN# valid
Min.
52 52 52 52
Typ.
Max.
Unit
ns ns ns ns
9.5.2 Interrupt Request Timing
ACK#
t1
t2
IRQx
Table 9-15. Interrupt Request Timing of Parallel Port Timing Symbol
t1 t2
Parameter
Delay from ACK# to IRQx Delay from ACK# to IRQx
Min.
Typ.
Max.
32 16
Unit
ns ns
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9.6 EPP Address or DATA WRITE Cycle
A[ 15:0 ] AEN
D[ 7:0 ]
IOW# t7
IOCHRDY t1
WRITE# t2 t6 t8 t10
ASTB# DSTB# t3 t5 t9
WAIT#
t4
PD[ 7:0 ]
Table 9-16. EPP Address or DATA WRITE Cycle Symbol
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Parameter
IOW# asserted to IOCHRDY asserted IOW# asserted to WRITE# asserted IOW# asserted to ASTB# or DSTB# asserted WRITE# asserted to PD[7:0] valid ASTB# or DSTB# asserted to WAIT# deasserted WAIT# deasserted to ASTB# or DSTB# deasserted WAIT# deasserted to IOCHRDY asserted ASTB# or DSTB# deasserted to WAIT# asserted WAIT# asserted to WRITE# deasserted PD[7:0] invalid after WRITE# deasserted
Min.
10 10 10
Typ.
Max.
70 70 70 70
Unit
ns ns ns ns us ns ns ns ns ns
0 65 65 0 65 0
10 135 135
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9.7 EPP Address or DATA READ Cycle
AEN A[ 15:0 ]
D[ 7:0 ] t10
IOR# t1 t7 IOCHRDY
WRITE# t2
ASTB# DSTB# t3 t6 t8
WAIT# t5 t9
t4
PD[ 7:0 ]
79
IT8661F
Table 9-17. EPP Address or DATA READ Cycle Symbol
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Parameter
IOR# asserted to IOCHRDY asserted IOR# asserted to ASTB# or DSTB# asserted ASTB# or DSTB# asserted to WAIT# deasserted ASTB# or DSTB# asserted to PD[7:0] Hi-Z PD[7:0] to WAIT# deasserted WAIT# deasserted to ASTB# or DSTB# deasserted WAIT# deasserted to IOCHRDY deasserted ASTB# or DSTB# deasserted to WAIT# deasserted PD[7:0] invalid after ASTB# or DSTB# deasserted D[7:0] invalid after IOR# deasserted
Min.
10 10
Typ.
Max.
70 70 10
Unit
ns ns us ns ns
0 0 65 65 0 20 0 25 135 135
ns ns ns ns ns
9.8 ECP Parallel Port Forward Timing Diagram
PD[7:0] nAutoFd t1 t5
nStrobe
t2
t3
t4
t6
Busy
80
IT8661F
Table 9-18. ECP Parallel Port Forward Timing Symbol
t1 t2 t3 t4 t5 t6
Parameter
PD[7:0] & nAutoFd valid to nStrobe asserted nStrobe asserted to busy asserted Busy asserted to nStrobe deasserted (see note) nStrobe deasserted to busy deasserted Busy deasserted to PD[7:0] & nAutoFd changed (see note) Busy deasserted to nStrobe asserted (see note)
Min.
0 0 80 0 80 80
Typ.
Max.
Unit
ns ns
180
ns ns
180 180
ns ns
Note: Maximum value only applies if there is data in the FIFO waiting to be written out.
9.9 ECP Parallel Port Backward Timing Diagram
PD[7:0] Busy t1 t5
nAck
t2
t3
t4
t6
nAutoFd
Table 9-19. ECP Parallel Port Backward Timing Symbol
t1 t2 t3 t4 t5 t6
Parameter
PD[7:0] & busy valid to nAck asserted nAck asserted to nAutoFd asserted (see note) nAutoFd asserted to nAck deasserted nAck deasserted to nAutoFd deasserted (see note) nAutoFd deasserted to PD[7:0] & busy changed nAutoFd deasserted to nAck asserted
Min.
0 80 0 80 90 0
Typ.
Max.
Unit
ns
210
ns ns
170
ns ns ns
Note: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nAUTOFD low.
81
IT8661F
10. Package Information
QFP 100L Outline Dimensions
HD D
100 81
unit: inches/mm
1
80
30
51
31
e
b 50 c
GE
HE
E
F
GD ~ ~ ~
GD A2 See Detail F Seating Plane A1
A
y
D
L L1
Detail F
Symbol A A1 A2 b c D E e F GD GE HD HE L L1 y
Dimension in inches 0.130 Max. 0.004 Min. 0.112 0.005 0.012 +0.004 -0.002 0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.026 0.006 0.742 NOM. 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.006 Max. 0 ~ 12
Dimension in mm 3.30 Max. 0.10 Min. 2.85 0.13 0.31 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 0.65 0.15 18.85 NOM. 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max. 0 ~ 12
Notes: 1. Dimensions D&E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.
82
IT8661F
11. Ordering Information
Part No.
IT8661F
Package
100L QFP
83

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